M29DW127G
128-Mbit (8 Mbit x16 or 16 Mbit x8 , multiple bank, page, dual boot)
3 V supply flash memory
Features
Supply voltage
– VCC = 2.7 to 3.6 V for program, erase and
read
– VCCQ = 1.65 to 3.6 V for I/O buffers
– VPPH = 12 V for fast program (optional)
Asynchronous random/page read
– Page width: 8 words / 16 bytes
– Page access: 25 ns
– Random access: 60 or 70, 80 ns
TSOP56 (NF)
14 x 20 mm
BGA
Enhanced Buffered Program commands
– 256 words
Programming time
– 15 μs per byte/word (typical)
– 32-word write buffer
– Chip program time: 5 s with VPPH and 8 s
without VPPH
Erase verify
Memory blocks
– Quadruple bank memory array:
16 Mbit+48 Mbit+48 Mbit+16 Mbit
– Parameter blocks (at top and bottom)
Dual operation
– while program or erase in one bank, read in
any of the other banks
Program/erase suspend and resume modes
– Read from any block during program
suspend
– Read and program another block during
erase suspend
Unlock Bypass/Block Erase/Chip Erase/Write
to Buffer/ Enhanced Buffered Program
commands
– Faster production/batch programming
– Faster block and chip erase
Common flash interface
– 64-bit security code
May 2009
TBGA64 (ZA)
10 x 13 mm
100,000 program/erase cycles per block
Low power consumption
– Standby and automatic standby
Hardware block protection
– VPP/WP pin for fast program and write
protect of the four outermost parameter
blocks
Security features
– Volatile protection
– Non-volatile protection
– Password protection
– Additional block protection
Extended memory block
– Extra block (128-word / 256-byte factory
locked and 128-word / 256-byte customer
lockable) used as security block or to store
additional information
Electronic signature
– Manufacturer code: 0020h
– Device code: 227Eh+2220h+2204h
ECOPACK® packages available
Rev 3
1/95
www.numonyx.com
1
Contents
M29DW127G
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
4
5
2/95
2.1
Address inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2
Data inputs/outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3
Data inputs/outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4
Data inputs/outputs or address inputs (DQ15A-1) . . . . . . . . . . . . . . . . . . 14
2.5
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.8
VPP/write protect (VPP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.9
Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.10
Ready/busy output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.11
Byte/word organization select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.12
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.13
VCCQ input/output supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.14
Vss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1
Bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2
Bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3
Output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6
Automatic standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Auto select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1
Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2
Verify extended memory block protection indicator . . . . . . . . . . . . . . . . . 21
4.3
Verify block protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
M29DW127G
5.1
6
Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Software protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1
Volatile protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.2
Non-volatile protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3
7
Contents
6.2.1
Non-volatile protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2.2
Non-volatile protection bit lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Password protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1
7.2
7.3
Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1.1
Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1.2
Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1.3
Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1.4
Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1.5
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1.6
Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1.7
Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1.8
Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1.9
Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1.10
Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Fast program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2.1
Write to Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2.2
Enhanced Buffered Program command . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.3
Buffered Program Abort and Reset command . . . . . . . . . . . . . . . . . . . . 37
7.2.4
Write to Buffer Program Confirm command . . . . . . . . . . . . . . . . . . . . . . 38
7.2.5
Enhanced Buffered Program Confirm command . . . . . . . . . . . . . . . . . . 38
7.2.6
Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.2.7
Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2.8
Unlock Bypass Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2.9
Unlock Bypass Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2.10
Unlock Bypass Write to Buffer Program command . . . . . . . . . . . . . . . . 40
7.2.11
Unlock Bypass Enhanced Buffered Program command . . . . . . . . . . . . 40
7.2.12
Unlock Bypass CFI command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.2.13
Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3/95
Contents
8
M29DW127G
7.3.1
Enter Extended Memory Block command . . . . . . . . . . . . . . . . . . . . . . . 43
7.3.2
Exit Extended Memory Block command . . . . . . . . . . . . . . . . . . . . . . . . 43
7.3.3
Lock register command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.3.4
Password protection mode command set . . . . . . . . . . . . . . . . . . . . . . . 44
7.3.5
Non-volatile protection mode command set . . . . . . . . . . . . . . . . . . . . . 45
7.3.6
NVPB lock bit command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.3.7
Volatile protection mode command set . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.3.8
Exit protection command set command . . . . . . . . . . . . . . . . . . . . . . . . . 47
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.1
8.2
8.3
Lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.1.1
Volatile lock boot bit (DQ4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.1.2
Password protection mode lock bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . 51
8.1.3
Non-volatile protection mode lock bit (DQ1) . . . . . . . . . . . . . . . . . . . . . 51
8.1.4
Extended block protection bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.1.5
DQ15 to DQ5 and DQ3 reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.2.1
Data polling bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.2.2
Toggle bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.2.3
Error bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.2.4
Erase timer bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.2.5
Alternative toggle bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Buffered program abort bit (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9
Dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 59
10
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
11
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
13
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Appendix A Block addresses and read/modify protection groups . . . . . . . . . . 81
Appendix B Common flash interface (CFI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4/95
M29DW127G
Contents
Appendix C Extended memory block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
C.1
Factory locked section of extended memory block . . . . . . . . . . . . . . . . . . 90
C.2
Customer lockable section of extended memory block . . . . . . . . . . . . . . . 91
Appendix D Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5/95
List of tables
M29DW127G
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
6/95
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VPP/WP functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bus operations, 8-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Bus operations, 16-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read electronic signature, auto select mode method (8-bit mode) . . . . . . . . . . . . . . . . . . 22
Read electronic signature, auto select mode method (16-bit mode) . . . . . . . . . . . . . . . . . 22
Block protection (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Block protection (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Standard commands (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Standard commands (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Fast program commands (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Fast program commands (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Enhanced buffered program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Block protection commands (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Block protection commands (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . 50
Lock register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Block protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Power-up waiting timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Write AC characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Write AC characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Accelerated program and data polling/data toggle AC characteristics . . . . . . . . . . . . . . . . 77
TSOP56 – 56 lead plastic thin small outline, 14 x 20 mm, package mechanical data . . . . 78
TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package mechanical data. . . . 79
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Extended memory block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
M29DW127G
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block addresses (x8 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block addresses (x16 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Software protection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
NVPB program/erase algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Lock register program flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Power-up waiting timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Random read AC waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Random read AC waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
BYTE transition AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Page read AC waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Page read AC waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Write enable controlled program waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . 70
Write enable controlled program waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . 71
Chip enable controlled program waveforms (8-bit mode). . . . . . . . . . . . . . . . . . . . . . . . . . 73
Chip enable controlled program waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . 74
Reset AC waveforms (no program/erase ongoing). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Reset during program/erase operation AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Accelerated program timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Data polling AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
TSOP56 – 56 lead plastic thin small outline, 14 x 20 mm, package outline . . . . . . . . . . . . 78
TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package outline . . . . . . . . . . . 79
Write to buffer program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Enhanced buffered program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7/95
Description
1
M29DW127G
Description
The M29DW127G is a 128-Mbit (8 Mbit x16 / 16 Mbit x8) non-volatile memory that can be
read, erased and reprogrammed. These operations can be performed using a single low
voltage (2.7 to 3.6 V) supply. At power-up the memory defaults to its read mode.
The M29DW127G features an asymmetrical block architecture, with 8 parameter and 62
main blocks, divided into four banks, A, B, C and D, providing multiple bank operations.
While programming or erasing in one bank, read operations are possible in any other bank.
The bank architecture is summarized in Table 2. Four of the parameter blocks are at the top
of the memory address space, and four are at the bottom.
Program and erase commands are written to the command interface of the memory. An onchip program/erase controller simplifies the process of programming or erasing the memory
by taking care of all of the special operations that are required to update the memory
contents. The end of a program or erase operation can be detected and any error conditions
identified. The command set required to control the memory is consistent with JEDEC
standards.
The Chip Enable, Output Enable and Write Enable signals control the bus operations of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The device supports asynchronous random read and page read from all blocks of the
memory array. The device also features a write to buffer program capability that improves
the programming throughput by programming in one shot a buffer of 32 words / 64 bytes.
The enhanced buffered program feature is also available to speed up programming
throughput, allowing 256 words to be programmed at once (only available in x16 mode).
The VPP/WP signal can be used to enable faster programming of the device.
The M29DW127G has one extra 256-word block in x16 mode or one extra 512-byte block in
x8 mode (extended block, 128 words / 256 bytes factory locked and 128 words / 256 bytes
customer lockable) that can be accessed using a dedicated command. The extended block
can be protected and so is useful for storing security information. However the protection is
irreversible, once protected the protection cannot be undone.
Each block can be erased independently, so it is possible to preserve valid data while old
data is erased.
The device features different levels of hardware and software block protection to avoid
unwanted program or erase (modify):
Hardware protection
–
The VPP/WP provides a hardware protection of the four outermost parameter
blocks (two at the top and two at the bottom of the address space)
Software protection
–
Volatile protection
–
Non-volatile protection
–
Password protection
Additional protection features are available upon customer request.
The memory is offered in TSOP56 (14 x 20 mm) and TBGA64 (10 x 13 mm, 1 mm pitch)
packages. The memory is delivered with all the bits erased (set to ‘1’).
8/95
M29DW127G
Description
Table 1.
Signal names
Name
A0-A22
Description
Direction
Address inputs
Inputs
DQ0-DQ7
Data inputs/outputs
I/O
DQ8-DQ14
Data inputs/outputs
I/O
DQ15A−1
Data input/output or address input
I/O
E
Chip enable
Input
G
Output enable
Input
W
Write enable
Input
RP
Reset
Input
RB
Ready/busy output
Output
BYTE
Byte/word organization select
VCCQ
Input/output buffer supply voltage
Supply
Supply voltage
Supply
VCC
VPP /WP(1)
Input
VPP/write protect
Supply/Input
VSS
Ground
–
NC
Not connected
–
1. VPP/WP may be left floating as it is internally connected to a pull-up resistor which enables program/erase
operations.
Figure 1.
Logic diagram
VCC VCCQ VPP/WP
23
15
A0-A22
DQ0-DQ14
DQ15A-1
W
E
G
RB
RP
BYTE
VSS
LogicDiagram-M29DWxx
9/95
Description
M29DW127G
Table 2.
Bank architecture
Parameter blocks
Bank
Main blocks
Bank size
N. of blocks
Block size
N. of blocks
Block size
A
16 Mbit
4
32 Kwords /
64 Kbytes
7
128 Kwords /
256 Kbytes
B
48 Mbit
—
—
24
128 Kwords /
256 Kbytes
C
48 Mbit
—
—
24
128 Kwords /
256 Kbytes
D
16 Mbit
4
32 Kwords /
64 Kbytes
7
128 Kwords /
256 Kbytes
Figure 2.
TSOP connections
NC
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
W
RP
A21
VPP/WP
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC
1
56
14
15
43
42
28
29
NC
NC
A16
BYTE
VSS
DQ15A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
NC
VCCQ
TSOP-Connections-M29DWxx
10/95
M29DW127G
Description
Figure 3.
TBGA connections (top view through package)
6
7
8
W
A9
A13
NC
VPP/WP
RP
A8
A12
A22
A6
A18
A21
A10
A14
NC
A1
A5
A20
A19
A11
A15
VCCQ
A0
DQ0
DQ2
DQ5
DQ7
A16
VSS
E
DQ8
DQ10
DQ12
DQ14
BYTE
NC
G
DQ9
DQ11
VCC
DQ13
DQ15
A-1
NC
VSS
DQ1
DQ3
DQ4
DQ6
VSS
NC
1
2
3
4
5
A
NC
A3
A7
RB
B
NC
A4
A17
C
NC
A2
D
NC
E
NC
F
VCCQ
G
NC
H
NC
AI11527c
11/95
Description
Figure 4.
M29DW127G
Block addresses (x8 mode)
Address lines A22-A0, DQ15A-1
800000h
000000h
64 Kbytes
256 Kbytes
83FFFFh
00FFFFh
Total of 4
parameter
blocks
Total of 24
main blocks
Bank C
DC0000h
030000h
64 Kbytes
Bank A
256 Kbytes
DFFFFFh
E00000h
03FFFFh
040000h
256 Kbytes
256 Kbytes
E3FFFFh
07FFFFh
Total of 7
main blocks
Total of 7
main blocks
F80000h
1C0000h
256 Kbytes
256 Kbytes
1FFFFFh
200000h
Bank D
FBFFFFh
FC0000h
256 Kbytes
64 Kbytes
FCFFFFh
23FFFFh
Total of 4
parameter
blocks
Total of 24
main blocks
Bank B
FF0000h
7C0000h
64 Kbytes
256 Kbytes
7FFFFFh
FFFFFFh
AI08967c
12/95
M29DW127G
Figure 5.
Description
Block addresses (x16 mode)
Address lines A22-A0
400000h
000000h
32 Kwords
128 Kwords
41FFFFh
007FFFh
Total of 4
parameter
blocks
Total of 24
main blocks
Bank C
6E0000h
018000h
32 Kwords
Bank A
128 Kwords
6FFFFFh
700000h
01FFFFh
020000h
128 Kwords
128 Kwords
71FFFFh
03FFFFh
Total of 7
main blocks
Total of 7
main blocks
7C0000h
0E0000h
128 Kwords
128 Kwords
0FFFFFh
100000h
Bank D
7DFFFFh
7E0000h
128 Kwords
32 Kwords
7E7FFFh
11FFFFh
Total of 4
parameter
blocks
Total of 24
main blocks
Bank B
7F8000h
3E0000h
32 Kwords
128 Kwords
3FFFFFh
7FFFFFh
AI08967b
13/95
Signal descriptions
2
M29DW127G
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names for a brief overview of the signals
connected to this device.
2.1
Address inputs (A0-A22)
The address inputs select the cells in the memory array to access during bus read
operations. During bus write operations they control the commands sent to the command
interface of the program/erase controller.
2.2
Data inputs/outputs (DQ0-DQ7)
The data I/O outputs the data stored at the selected address during a bus read operation.
During bus write operations they represent the commands sent to the command interface of
the internal state machine.
2.3
Data inputs/outputs (DQ8-DQ14)
The data I/O outputs the data stored at the selected address during a bus read operation
when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high
impedance. During bus write operations the command register does not use these bits.
When reading the status register these bits should be ignored.
2.4
Data inputs/outputs or address inputs (DQ15A−1)
When the device is in x 16 bus mode, this pin behaves as a data input/output pin (as DQ8DQ14). When the device operates in x 8 bus mode, this pin behaves as the least significant
bit of the address. Throughout the text consider references to the data input/output to
include this pin when the device operates in x 16 bus mode and references to the address
inputs to include this pin when the device operates in x 8 bus mode except when stated
explicitly otherwise.
2.5
Chip Enable (E)
The Chip Enable pin, E, activates the memory, allowing bus read and bus write operations
to be performed. When chip enable is High, VIH, all other pins are ignored.
2.6
Output Enable (G)
The Output Enable pin, G, controls the bus read operation of the memory.
14/95
M29DW127G
2.7
Signal descriptions
Write Enable (W)
The Write Enable pin, W, controls the bus write operation of the memory’s command
interface.
2.8
VPP/write protect (VPP/WP)
The VPP/write protect pin provides two functions. The VPPH function allows the memory to
use an external high voltage power supply to reduce the time required for program
operations. This is achieved by bypassing the unlock cycles.
The write protect function provides a hardware method of protecting the four outermost
blocks, that is the two 32-kword blocks at the top and the two 32-kword blocks at the bottom
of the address space (see Section 1: Description). When VPP/write protect is Low, VIL, the 4
outermost blocks are protected. Program and erase operations on this block are ignored
while VPP/write protect is Low.
When VPP /write protect is High, VIH, the memory reverts to the previous protection status of
the four outermost blocks. Program and erase operations can now modify the data in these
blocks unless the blocks are protected using block protection.
When VPP/write protect is raised to VPPH the memory automatically enters the unlock
bypass mode (see Section 7.2.6).
When VPP /write protect is raised to VPPH, the execution time of the command is lower (see
Table 18: Program, erase times and program, erase endurance cycles).
When VPP/write protect returns to VIH or VIL normal operation resumes. During unlock
bypass program operations the memory draws IPP from the pin to supply the programming
circuits. See the description of the Unlock Bypass command in the command interface
section. The transitions from VIH to VPPH and from VPPH to VIH must be slower than tVHVPP
(see Figure 25: Accelerated program timing waveforms).
Never raise VPP/write protect to VPPH from any mode except read mode, otherwise the
memory may be left in an indeterminate state. A 0.1 μF capacitor should be connected
between the VPP/write protect pin and the VSS ground pin to decouple the current surges
from the power supply. The PCB track widths must be sufficient to carry the currents
required during unlock bypass program (see IPP1, IPP2, IPP3, IPP4 in Table 28: DC
characteristics).
The VPP/write protect pin may be left floating or unconnected because it features an internal
pull-up.
Refer to Table 3 for a summary of VPP/WP functions.
Table 3.
VPP/WP functions
VPP/WP
Function
VIL
Four outermost blocks(1) protected.
VIH
Four outermost blocks(1) unprotected unless a software protection is
activated (see Section 5: Hardware protection).
VPPH
Unlock bypass mode. It supplies the current needed to speed up
programming.
1. Two at the top and two at the bottom of the address space.
15/95
Signal descriptions
2.9
M29DW127G
Reset (RP)
The reset pin can be used to apply a hardware reset to the memory.
A hardware reset is achieved by holding reset Low, VIL, for at least tPLPX. After reset goes
High, VIH, the memory will be ready for bus read and bus write operations after tPHEL or
tRHEL, whichever occurs last. See Section 2.10: Ready/busy output (RB), Table 32: Reset
AC characteristics, Figure 23 and Figure 24 for more details.
2.10
Ready/busy output (RB)
The ready/busy pin is an open-drain output that can be used to identify when the device is
performing a program or erase operation. During program or erase operations ready/busy is
Low, VOL (see Table 21: Status register bits). Ready/busy is high-impedance during read
mode, auto select mode and erase suspend mode.
After a hardware reset, bus read and bus write operations cannot begin until ready/busy
becomes high-impedance. See Table 32: Reset AC characteristics, Figure 23 and
Figure 24.
The use of an open-drain output allows the ready/busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
2.11
Byte/word organization select (BYTE)
It is used to switch between the x8 and x16 bus modes of the memory. When byte/word
organization select is Low, VIL, the memory is in x8 mode, when it is High, VIH, the memory
is in x16 mode.
2.12
VCC supply voltage
VCC provides the power supply for all operations (read, program and erase).
The command interface is disabled when the VCC supply voltage is less than the lockout
voltage, VLKO. This prevents bus write operations from accidentally damaging the data
during power-up, power-down and power surges. If the program/erase controller is
programming or erasing during this time then the operation aborts and the memory contents
being altered will be invalid.
A 0.1 μF capacitor should be connected between the VCC supply voltage pin and the VSS
ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during program and erase operations (see
ICC1, ICC2, ICC3 in Table 28: DC characteristics).
2.13
VCCQ input/output supply voltage
VCCQ provides the power supply to the I/O pins and enables all outputs to be powered
independently from VCC.
16/95
M29DW127G
2.14
Signal descriptions
Vss ground
VSS is the reference for all voltage measurements. The device features two VSS pins both of
which must be connected to the system ground.
17/95
Bus operations
3
M29DW127G
Bus operations
There are five standard bus operations that control the device. These are bus read (random
and page modes), bus write, output disable, standby and automatic standby.
Dual operations are possible in the M29DW127G, thanks to its multiple bank architecture.
While programming or erasing in one bank, read operations are possible in any of the other
banks. Write operations are only allowed in one bank at a time.
See Table 4: Bus operations, 8-bit mode on page 20 and Table 5: Bus operations, 16-bit
mode on page 20 for a summary. Typical glitches of less than 5 ns on chip enable, write
enable, and reset pins are ignored by the memory and do not affect bus operations.
3.1
Bus read
Bus read operations read from the memory cells, or specific registers in the command
interface. To speed up the read operation the memory array can be read in page mode
where data is internally read and stored in a page buffer. The page has a size of 8 words (or
16 bytes) and is addressed by the address inputs A2-A0 in x16 mode and A2-A0 plus
DQ15A-1 in x8 mode.
A valid bus read operation involves setting the desired address on the address inputs,
applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable
High, VIH. The data inputs/outputs will output the value, see Figure 14: Random read AC
waveforms (8-bit mode) on page 65, Figure 15: Random read AC waveforms (16-bit mode)
on page 65, and Table 29: Read AC characteristics on page 69 for details of when the
output becomes valid.
3.2
Bus write
Bus write operations write to the command interface. A valid bus write operation begins by
setting the desired address on the address inputs. The address inputs are latched by the
command interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The data inputs/outputs are latched by the command interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH,
during the whole bus write operation.
For details on AC characteristics (write enabled and chip enabled controlled), see the
following figures and tables:
3.3
–
Figure 19: Write enable controlled program waveforms (8-bit mode) on page 70
–
Figure 20: Write enable controlled program waveforms (16-bit mode) on page 71
–
Table 30: Write AC characteristics, write enable controlled on page 72
–
Figure 21: Chip enable controlled program waveforms (8-bit mode) on page 73
–
Figure 22: Chip enable controlled program waveforms (16-bit mode) on page 74
–
Table 31: Write AC characteristics, chip enable controlled on page 74
Output disable
The data inputs/outputs are in the high impedance state when output enable is High, VIH.
18/95
M29DW127G
3.4
Bus operations
Standby
Driving Chip Enable High, VIH, in read mode, causes the memory to enter standby mode
and the data inputs/outputs pins are placed in the high-impedance state. To reduce the
supply current to the standby supply current, ICC2, Chip Enable should be held within
VCC ± 0.3 V. For the standby current level see Table 28: DC characteristics.
During program or erase operations the memory will continue to use the program/erase
supply current, ICC3, for program or erase operations until the operation completes.
3.5
Reset
During reset mode the memory is deselected and the outputs are high impedance. The
memory is in reset mode when RP is at VIL. The power consumption is reduced to the
standby level, independently from the Chip Enable, Output Enable or Write Enable inputs.
3.6
Automatic standby
Automatic standby allows the memory to achieve low power consumption during read
mode.
After a read operation, if CMOS levels (VCC ± 0.3 V) are used to drive the bus and the bus is
inactive for tAVQV + 30 ns or more, the memory enters automatic standby where the internal
supply current is reduced to the standby supply current, ICC2 (see Table 28: DC
characteristics). The data inputs/outputs will still output data if a bus read operation is in
progress.
The power supplier of data bus, VCCQ, can have a null consumption (depending on load
circuits connected with data bus) when the memory enters automatic standby.
19/95
Bus operations
Table 4.
M29DW127G
M
Bus operations, 8-bit mode
Operation(1)
Bus read
Address Inputs
E
G
VIL
VIL
W
VIH
RP
Data inputs/outputs
VPP /WP
VIH
X
(2)
DQ14-DQ8
DQ7-DQ0
Cell address
Hi-Z
Data output
Command address
Hi-Z
Data input(3)
Bus write
VIL
VIH
VIL
VIH
Standby
VIH
X
X
VIH
X
X
Hi-Z
Hi-Z
Output disable
VIL
VIH
VIH
VIH
X
X
Hi-Z
Hi-Z
X
X
X
VIL
X
X
Hi-Z
Hi-Z
Reset
X
A22-A0, DQ15A-1
1. X = VIL or VIH .
2. To write the four outermost parameter blocks (first two and the last two), VPP/WP must be equal to VIH.
3. Data input as required when issuing a command sequence, performing data polling or block protection.
Table 5.
Bus operations, 16-bit mode
Operation(1)
Bus read
E
VIL
G
VIL
W
VIH
Address inputs
Data inputs/outputs
A22-A0
DQ15A-1, DQ14-DQ0
Cell address
Data output
Command address
Data input(3)
RP VPP/WP
VIH
X
(2)
Bus write
VIL
VIH
VIL
VIH
Standby
VIH
X
X
VIH
X
X
Hi-Z
Output disable
VIL
VIH
X
X
Hi-Z
VIL
X
X
Hi-Z
Reset
X
VIH VIH
X
X
X
1. X = VIL or VIH .
2. To write the four outermost parameter blocks (first two and last two), VPP/WP must be equal to VIH.
3. Data input as required when issuing a command sequence, performing data polling or block protection.
20/95
M29DW127G
4
Auto select mode
Auto select mode
The auto select mode allows the system or the programming equipment to read the
electronic signature, verify the protection status of the extended memory block, and
apply/remove block protection. For example, this mode can be used by a programming
equipment to automatically match a device and the application code to be programmed.
The auto select mode is entered by issuing the Auto Select command (see Section 7.1.2:
Auto Select command).
At power-up, the device is in read mode, and can then be put in auto select mode by issuing
the Auto Select command.
The device cannot enter auto select mode when a program or erase operation is ongoing
(RB Low). However, auto select mode can be entered if the erase operation has been
suspended by issuing an Erase Suspend command (see Section 7.1.6).
The auto select mode is exited by performing a reset. The device is returned to read mode,
except if the auto select mode was entered after an Erase Suspend or a Program Suspend
command. In this case, it returns to the erase or program suspend mode.
4.1
Read electronic signature
The memory has two codes, the manufacturer code and the device code used to identify the
memory. These codes can be accessed by performing read operations with control signals
and addresses set as shown in Table 9: Block protection (16-bit mode) and Table 6: Read
electronic signature, auto select mode method (8-bit mode) and Table 7: Read electronic
signature, auto select mode method (16-bit mode).
4.2
Verify extended memory block protection indicator
The extended memory block is either factory locked or customer lockable.
The protection status of the extended memory block (factory locked or customer lockable)
can be accessed by reading the extended memory block protection indicator. See Table 8:
Block protection (8-bit mode) and Table 9.: Block protection (16-bit mode).
The protection status of the extended memory block is then output on bit DQ7 of the data
input/outputs (see Table 4: Bus operations, 8-bit mode and Table 5: Bus operations, 16-bit
mode).
4.3
Verify block protection status
The protection status of a block can be directly accessed by performing a read operation
with control signals and addresses set as shown in Table 8: Block protection (8-bit mode)
and Table 9: Block protection (16-bit mode).
If the block is protected, then 01h is output on data input/outputs DQ0-DQ7, otherwise 00h
is output.
21/95
Auto select mode
Table 6.
M29DW127G
Read electronic signature, auto select mode method (8-bit mode)
Address inputs
(1)
Read cycle
E
G
W
A22A10
A9A8 A6
A7
A5A4
Manufacturer
code
Device code
(cycle 1)
Device code
(cycle 2)
X
VIL VIL VIH
BKA
X
X
Data inputs/outputs
A2
A1
A0
DQ15A-1
DQ14DQ8
DQ7DQ0
VIL VIL
VIL
VIL
X
X
20h
VIL VIL
VIL
VIH
X
X
7Eh
VIH VIH VIH
VIL
X
X
20h
VIH VIH VIH
VIH
X
X
04h
A3
VIL
VIL
Device code
(cycle 3)
1. X = VIL or VIH . BKA bank address.
Table 7.
Read electronic signature, auto select mode method (16-bit mode)
Data
inputs/outputs
Address inputs
Read
cycle(1)
E
G
W
A22A12
A11A10
A9
A8
A7-A6
Manufacturer
code
Device code
(cycle 1)
Device code
(cycle 2)
VIL VIL VIH
BKA
Device code
(cycle 3)
1. X = VIL or VIH . BKA bank address.
22/95
X
X
X
A5A4
A3
A2
A1
A0
DQ15-DQ0
X
VIL
VIL
VIL
VIL
0020h
VIL
VIL
VIL
VIH
227Eh
VIH
VIH
VIH
VIL
2220h
VIH
VIH
VIH
VIH
2204h
VIL
VIL
M29DW127G
Table 8.
Auto select mode
Block protection (8-bit mode)
Address inputs
Operation(1)
Verify
extended
memory block
protection
indicator
(bit DQ7)
E
G
W
A22A16
VIL VIL VIH BKA
Verify block
protection
status
A14A10
X
A9
X
A8A7
X
Data inputs/outputs
A5- A3A4 A2
A6
VIL
X
VIL
A1
DQ15 DQ14A-1
DQ8
A0
VIH VIH
BAd
X
X
DQ7-DQ0
DQ7: 1=factory locked
DQ6: 1=customer
locked,
0=customer lockable
DQ5: 1=reserved,
0=standard
DQ4, DQ3-Hardware
write
protection: 00=WP
protects 4
outermost blocks,
11=No WP
protection
DQ2-DQ0=0
01h (protected)
00h (unprotected)
VIL
1. X = VIL or VIH; BAd = any address in the block; BKA = bank address.
Table 9.
Block protection (16-bit mode)
Address inputs
Operation
(1)
Verify
extended
memory
block
indicator bit
Verify block
protection
status
E
VIL
G
W
VIL VIH
VPP/
RP
WP
VIH
VIH
A22A12
BKA
A11A10
X
A9
X
A8
X
BAd
A7
VIL
A6
VIL
Data inputs/outputs
A5A4
VIL
A3A2
VIL
A1
VIH
A0
DQ15-DQ0
VIH
DQ15-DQ8=0
DQ7: 1=factory locked
DQ6: 1=customer
locked, 0=customer
lockable
DQ5: 1=reserved,
0=standard
DQ4, DQ3-Hardware
write protection:
00=WP protects 4
outermost blocks,
11=No WP protection
DQ2-DQ0=0
VIL
0000h (unprotected)
0001h (protected)
1. X = VIL or VIH . BAd any address in the block, BKA bank address.
23/95
Hardware protection
5
M29DW127G
Hardware protection
The M29DW127G features hardware protection/unprotection. Refer to Table 10: Hardware
protection for details on hardware block protection/unprotection using VPP/WP and RP pins.
5.1
Write protect
The VPP/WP pin can be used to protect the four outermost parameter blocks (refer to
Section 2: Signal descriptions for a detailed description of the signals). When VPP/WP is at
VIL the four outermost parameter blocks are protected and remain protected regardless of
the block protection status or the reset pin state.
Table 10.
Hardware protection
VPP/WP
VIL
4 outermost parameter blocks (first two and last two) protected from
program/erase operations
VIH
4 outermost parameter blocks unprotected unless a software activated (see
Section 5: Hardware protection)
VPPH
24/95
Function
Unlock bypass mode. It supplies the current needed to speed up
programming
M29DW127G
6
Software protection
Software protection
The M29DW127G has three different software protection modes:
Volatile protection
Non-volatile protection
Password protection
On first use all parts default to operate in non-volatile protection mode and the customer is
free to activate the non-volatile or the password protection mode.
The desired protection mode is activated by setting either the one-time programmable nonvolatile protection mode lock bit or the password protection mode lock bit of the lock register
(see Section 8.1: Lock register). Programming the non-volatile protection mode lock bit or
the password protection mode lock bit to ‘0’ will permanently activate the non-volatile or the
password protection mode, respectively. These three bits are one-time programmable and
non-volatile: once the protection mode has been programmed, it cannot be changed and the
device will permanently operate in the selected protection mode. It is recommended to
activate the desired software protection mode when first programming the device.
The non-volatile and password protection modes provide non-volatile protection. Volatilely
protected blocks and non-volatilely protected blocks can co-exist within the memory array.
However, the volatile protection only control the protection scheme for blocks that are not
protected using the non-volatile or password protection.
If the user attempts to program or erase a protected block, the device ignores the command
and returns to read mode.
The device is shipped with all blocks unprotected. The block protection status can be read
either by performing a read electronic signature (see Table 7: Read electronic signature,
auto select mode method (16-bit mode)) or by issuing an Auto Select command (see
Table 20: Block protection status).
For the four outermost blocks (that is the two blocks at the top and the two at the bottom of
the address space), an even higher level of block protection can be achieved by locking the
blocks using the non-volatile protection and then by holding the VPP/WP pin Low.
6.1
Volatile protection mode
The volatile protection allows the software application to easily protect blocks against
inadvertent change. However, the protection can be easily disabled when changes are
needed. Volatile protection bits, VPBs, are volatile and unique for each block and can be
individually modified. VPBs only control the protection scheme for unprotected blocks that
have their non-volatile protection bits, NVPBs, cleared (erased to ‘1’) (see Section 6.2: Nonvolatile protection mode and Section 7.3.5: Non-volatile protection mode command set).
By issuing the VPB Program or VPB Clear commands, the VPBs are set (programmed to
‘0’) or cleared (erased to ‘1’), thus placing each block in the protected or unprotected state
respectively. The VPBs can be set (programmed to ‘0’) or cleared (erased to ‘1’) as often as
needed.
The default values of the volatile protections are set through the VLBB (volatile lock boot bit)
of the lock register (see Table 19: Lock register bits).
25/95
Software protection
M29DW127G
When the parts are first shipped, or after a power-up or hardware reset, the VPBs can be set
or cleared depending upon the ordering option chosen:
If the option to clear the VPBs after power-up is selected, then the blocks can be
programmed or erased depending on the NVPBs state (see Table 20: Block protection
status)
If the option to set the VPBs after power-up is selected, the blocks default to be
protected.
Refer to Section 7.3.7 for a description of the volatile protection mode command set.
6.2
Non-volatile protection mode
6.2.1
Non-volatile protection bits
A non-volatile protection bit (NVPB) is assigned to each block.
When a NVPB is set to ‘0’, the associated block is protected, preventing any program or
erase operations in this block.
The NVPB bits are set individually by issuing a NVPB Program command. They are nonvolatile and will remain set through a hardware reset or a power-down/power-up sequence.
The NVPBs cannot be cleared individually, they can only be cleared all at the same time by
issuing a Clear all Non-volatile Protection Bits command.
The NVPBs can be protected all at a time by setting a volatile bit, the NVPB lock bit (see
Section 6.2.2: Non-volatile protection bit lock bit).
If one of the non-volatile protected blocks needs to be unprotected (corresponding NVPB
set to ‘1’), a few more steps are required:
1.
2.
3.
Note:
First, the NVPB lock bit must be cleared by either putting the device through a power
cycle, or hardware reset
The NVPBs can then be changed to reflect the desired settings
The NVPB lock bit must be set once again to lock the NVPBs. The device operates
normally again.
1
To achieve the best protection, it is recommended to execute the NVPB Lock Bit Program
command early in the boot code and to protect the boot code by holding VPP/WP Low, VIL.
2
The NVPBs and VPBs have the same function when VPP/WP pin is High, VIH, as they do
when VPP /WP pin is at the voltage for program acceleration (VPPH).
Refer to Table 20: Block protection status and Figure 6: Software protection scheme for
details on the block protection mechanism, and to Section 7.3.5 for a description of the nonvolatile protection mode command set.
6.2.2
Non-volatile protection bit lock bit
The non-volatile protection bit lock bit (NVPB lock bit) is a global volatile bit for all blocks.
When set (programmed to ‘0’), it prevents changing the state of the NVPBs. When cleared
(programmed to ‘1’), the NVPBs can be set and reset using the NVPB Program command
and Clear all NVPBs command, respectively.
There is only one NVPB lock bit per device.
26/95
M29DW127G
Software protection
Refer to Section 7.3.6 for a description of the NVPB lock bit command set.
Note:
6.3
1
No software command unlocks this bit unless the device is in password protection mode; it
can be cleared only by taking the device through a hardware reset or a power-up.
2
The NVPB lock bit must be set (programmed to ‘0’) only after all NVPBs are configured to
the desired settings.
Password protection mode
The password protection mode provides an even higher level of security than the nonvolatile protection mode by requiring a 64-bit password for unlocking the device NVPB lock
bit.
In addition to this password requirement, the NVPB lock bit is set ‘0’ after power-up and
reset to maintain the device in password protection mode. Successful execution of the
Password Unlock command by entering the correct password clears the NVPB lock bit,
allowing for block NVPBs to be modified.
If the password provided is not correct, the NVPL Lock bit remains locked and the state of
the NVPBs cannot be modified.
To place the device in password protection mode, the following steps are required:
1.
Prior to entering the password protection mode, it is necessary to set a 64-bit password
and to verify it (see Password Program command and Password Read command).
Password verification is only allowed during the password programming operation
2.
The password protection mode is then activated by programming the password
protection mode lock bit to ‘0’. This operation is not reversible and once the bit is
programmed it cannot be erased, the device permanently remains in password
protection mode, and the 64-bit password can neither be retrieved nor reprogrammed.
Moreover, all commands to the address where the password is stored, are disabled.
Refer to Table 20: Block protection status and Figure 6: Software protection scheme for
details on the block protection scheme.
Refer to Section 7.3.4 for a description of the password protection mode command set.
Note:
There is no means to verify the password after it is set. If the password is lost after setting
the password mode lock bit, there is no way to clear the NVPB lock bit.
27/95
Software protection
Figure 6.
M29DW127G
Software protection scheme
VPB(2)
Parameter block or
main block
Volatile protection
NVPB(1)
NVPB Lock bit(3)
Non-volatile protection
Non-volatile
protection mode
Password protection
mode
AI13676
1. NVPBs default to ‘1’ (block unprotected) after power-up and hardware reset. A block is protected or unprotected when its
NVPB is set to ‘0’ and ‘1’, respectively. NVPBs are programmed individually and cleared collectively.
2. VPB default status depends on ordering option. A block is protected or unprotected when its VPB is set to ‘0’ and ‘1’,
respectively. VPBs are programmed and cleared individually. For the volatile protection to be effective, the NVPB lock bit
must be set to ‘0’ (NVPB bits unlocked) and the block NVPB must be set to ‘1’ (block unprotected).
3. The NVPB Lock bit is volatile and default to ‘1’ (NVPB bits unlocked) after power-up and hardware reset. NVPB bits are
locked by setting the NVPB lock bit to ‘0’. Once programmed to ‘0’, the NVPB lock bit can be reset to ‘1’ only be taking the
device through a power-up or hardware reset.
28/95
M29DW127G
7
Command interface
Command interface
All bus write operations to the memory are interpreted by the command interface.
Commands consist of one or more sequential bus write operations. Failure to observe a
valid sequence of bus write operations will result in the memory returning to read mode. The
long command sequences are imposed to maximize data security.
7.1
Standard commands
See Table 12: Standard commands (16-bit mode) for a summary of the standard
commands.
7.1.1
Read/Reset command
The device is in read mode after reset or after power-up.
The Read/Reset command returns the memory to read mode. It also resets the errors in the
status register. Either one or three bus write operations can be used to issue the
Read/Reset command.
The Read/Reset command can be issued, between bus write cycles before the start of a
program or erase operation, to return the device to read mode. If the Read/Reset command
is issued during the timeout of a block erase operation, the memory will take up to 10 μs to
abort. During the abort period no valid data can be read from the memory.
The Read/Reset command will not abort an erase operation when issued while in erase
suspend.
7.1.2
Auto Select command
The Auto Select command puts the device in auto select mode (see Section 4: Auto select
mode). When in auto select mode, the system can read the manufacturer code, the device
code, the protection status of each block (block protection status) and the extended memory
block protection indicator.
Three consecutive bus write operations are required to issue the Auto Select command.
Once the Auto Select command is issued bus read operations to specific addresses output
the manufacturer code, the device code, the extended memory block protection indicator
and a block protection status (see Table 12: Standard commands (16-bit mode) in
conjunction with Table 7: Read electronic signature, auto select mode method (16-bit
mode), and Table 9: Block protection (16-bit mode)). The memory remains in auto select
mode until a Read/Reset or CFI Query command is issued.
29/95
Command interface
7.1.3
M29DW127G
Read CFI Query command
The memory contains an information area, named CFI data structure, which contains a
description of various electrical and timing parameters, density information and functions
supported by the memory. See Appendix B, Table 38, Table 39, Table 40, Table 41,
Table 42 and Table 43 for details on the information contained in the common flash interface
(CFI) memory area.
The Read CFI Query command is used to put the memory in read CFI query mode. Once in
read CFI query mode, bus read operations to the memory will output data from the common
flash interface (CFI) memory area. One bus write cycle is required to issue the Read CFI
Query command. This command is valid only when the device is in the read array or auto
select mode.
The Read/Reset command must be issued to return the device to the previous mode (the
read array mode or auto select mode). A second Read/Reset command is required to put
the device in read array mode from auto select mode.
7.1.4
Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six bus write operations are
required to issue the Chip Erase command and start the program/erase controller.
If some block are protected, then these are ignored and all the other blocks are erased. If all
of the blocks are protected the chip erase operation appears to start but will terminate within
about 100 μs, leaving the data unchanged. No error condition is given when protected
blocks are ignored.
During the erase operation the memory will ignore all commands, including the Erase
Suspend command. It is not possible to issue any command to abort the operation. Typical
chip erase times are given in Table 18. All bus read operations during the chip erase
operation will output the status register on the data inputs/outputs. See Section 8.2: Status
register for more details.
After the chip erase operation has completed the memory will return to the read mode,
unless an error has occurred. When an error occurs the memory will continue to output the
status register. A Read/Reset command must be issued to reset the error condition and
return to read mode.
The Chip Erase command sets all of the bits in unprotected blocks of the memory to ’1’. All
previous data is lost.
The chip erase operation is aborted by performing a reset or powering down the device. In
this case, data integrity cannot be ensured, and it is recommended to erase again the entire
chip.
7.1.5
Block Erase command
The Block Erase command can be used to erase a list of one or more blocks. It sets all of
the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is
lost.
Six bus write operations are required to select the first block in the list. Each additional block
in the list can be selected by repeating the sixth bus write operation using the address of the
additional block. After the command sequence is written, a block erase timeout occurs.
During the timeout period, additional sector addresses and sector erase commands may be
written. Once the program/erase controller has started, it is not possible to select any more
30/95
M29DW127G
Command interface
blocks. Each additional block must therefore be selected within the timeout period of the last
block. The timeout timer restarts when an additional block is selected. After the sixth bus
write operation, a bus read operation outputs the status register (bus reading operations
from banks different from those including the blocks being erased, output the memory array
content). See Figure 19: Write enable controlled program waveforms (8-bit mode) and
Figure 20: Write enable controlled program waveforms (16-bit mode) for details on how to
identify if the program/erase controller has started the block erase operation.
After the block erase operation has completed, the memory returns to the read mode,
unless an error has occurred. When an error occurs, bus read operations will continue to
output the status register. A Read/Reset command must be issued to reset the error
condition and return to read mode.
If any selected blocks are protected then these are ignored and all the other selected blocks
are erased. If all of the selected blocks are protected the block erase operation appears to
start but will terminate within about 100 μs, leaving the data unchanged. No error condition
is given when protected blocks are ignored.
During the block erase operation the memory ignores all commands except the Erase
Suspend command and the Read/Reset command which is only accepted during the
timeout period. Typical block erase time and block erase timeout are given in Table 18.
The block erase operation is aborted by performing a reset or powering down the device. In
this case, data integrity cannot be ensured, and it is recommended to erase again the
blocks aborted.
7.1.6
Erase Suspend command
The Erase Suspend command can be used to temporarily suspend a block erase operation.
One bus write operation is required to issue the command together with the block address.
The program/erase controller suspends the erase operation within the erase suspend
latency time of the Erase Suspend command being issued. However, when the Erase
Suspend command is written during the block erase timeout, the device immediately
terminates the timeout period and suspends the erase operation.
Once the program/erase controller has stopped, the memory operates in read mode and the
erase is suspended.
During erase suspend it is possible to read and execute program or write to buffer program
operations in blocks that are not suspended; both read and program operations behave as
normal on these blocks. Reading from blocks that are suspended will output the status
register. If any attempt is made to program in a protected block or in the suspended block
then the Program command is ignored and the data remains unchanged. In this case the
status register is not read and no error condition is given.
It is also possible to issue the Auto Select (after entering Autoselect mode), Read CFI
Query, and Unlock Bypass commands during an erase suspend. The Read/Reset command
must be issued to return the device to read array mode before the Resume command will be
accepted.
During erase suspend a bus read operation to the extended memory block will output the
extended memory block data. Once in the extended block mode, the Exit Extended Block
command must be issued before the erase operation can be resumed.
The Erase Suspend command is ignored if written during chip erase operations.
31/95
Command interface
M29DW127G
Refer to Table 18: Program, erase times and program, erase endurance cycles for the
values of block erase timeout and block erase suspend latency time.
If the erase suspend operation is aborted by performing a reset or powering down the
device, data integrity cannot be ensured, and it is recommended to erase again the blocks
suspended.
7.1.7
Erase Resume command
The Erase Resume command is used to restart the program/erase controller after an erase
suspend.
The device must be in read array mode before the Resume command will be accepted. An
erase can be suspended and resumed more than once.
7.1.8
Program Suspend command
The Program Suspend command allows the system to interrupt a program operation so that
data can be read from any block. When the Program Suspend command is issued during a
program operation, the device suspends the program operation within the program suspend
latency time (see Table 18: Program, erase times and program, erase endurance cycles)
and updates the status register bits.
After the program operation has been suspended, the system can read array data from any
address. However, data read from program-suspended addresses is not valid.
The Program Suspend command may also be issued during a program operation while an
erase is suspended. In this case, data may be read from any addresses not in Erase
Suspend or Program Suspend. If a read is needed from the extended memory block area
(one-time program area), the user must use the proper command sequences to enter and
exit this region.
The system may also issue the Auto Select command sequence when the device is in the
program suspend mode. The system can read as many auto select codes as required.
When the device exits the auto select mode, the device reverts to the program suspend
mode, and is ready for another valid operation. See Auto Select command sequence for
more information.
If the program suspend operation is aborted by performing a reset or powering down the
device, data integrity cannot be ensured, and it is recommended to program again the
words or bytes aborted.
7.1.9
Program Resume command
After the Program Resume command is issued, the device reverts to programming. The
controller can determine the status of the program operation using the DQ7 or DQ6 status
bits, just as in the standard program operation. Refer to Figure 19: Write enable controlled
program waveforms (8-bit mode) and Figure 20: Write enable controlled program
waveforms (16-bit mode) for details.
The system must issue a Program Resume command, to exit the program suspend mode
and to continue the programming operation.
Further issuing of the Resume command is ignored. Another Program Suspend command
can be written after the device has resumed programming.
32/95
M29DW127G
7.1.10
Command interface
Program command
The Program command can be used to program a value in the memory array one address
at a time. The command requires four bus write operations, the final write operation latches
the address and data in the internal state machine and starts the program/erase controller.
Programming can be suspended and then resumed by issuing a Program Suspend
command and a Program Resume command, respectively. If the address falls in a protected
block, the Program command is ignored and the data remains unchanged. The status
register is never read and no error condition is given.
After programming has started, bus read operations output the status register content (bus
reading operations from banks different from those including the block being programmed,
output the memory array content). See Figure 19: Write enable controlled program
waveforms (8-bit mode) and Figure 20: Write enable controlled program waveforms (16-bit
mode) for more details. Typical program times are given in Table 18: Program, erase times
and program, erase endurance cycles.
After the program operation has completed the memory will return to the read mode, unless
an error has occurred. When an error occurs, bus read operations to the memory continue
to output the status register. A Read/Reset command must be issued to reset the error
condition and return to read mode.
One of the erase commands must be used to set all the bits in a block or in the whole
memory from ’0’ to ’1’.
The program operation is aborted by performing a reset or powering-down the device. In
this case data integrity cannot be ensured, and it is recommended to reprogram the word or
byte aborted.
33/95
Command interface
Table 11.
M29DW127G
Standard commands (8-bit mode)
Command(1)
Length
Bus operations (2)
1st
2nd
Add
Data
1
X
F0
3
AAA
3
Program (5)
3rd
4th
Add
Data
Add
Data
AA
555
55
X
F0
AAA
AA
555
55
(BKA)
AAA
4
AAA
AA
555
55
Chip Erase
6
AAA
AA
555
Block Erase
6+
AAA
AA
555
Erase/Program
Suspend
1
BKA
B0
Erase/Program
Resume
1
BKA
30
Read CFI Query
1
BKA
AAA
98
Read/Reset
5th
Add
Data
90
(3)(4)
(3)(4)
AAA
A0
PA
PD
55
AAA
80
AAA
55
AAA
80
AAA
6th
Add
Data
Add
Data
AA
555
55
AAA
10
AA
555
55
BAd
30
Manufacturer
code
Device code
Extended
Auto
memory block
Select protection
indicator
Block
protection
status
1. The device doesn’t tolerate FFh as a valid command, and once FFh is issued to the device, the M29DW127G will enter
unexpected state. Adding a F0h command systematically after FFh command is necessary.
2. X don’t care, PA program address, PD program data, BAd any address in block, BKA bank address, values hexadecimal.
3. These cells represent read cycles. All the other cells are write cycles.
4. The auto select addresses and data are given in Table 7: Read electronic signature, auto select mode method (16-bit
mode), and Table 9: Block protection (16-bit mode), except for A9 that is ‘don’t care’.
5. In unlock bypass, the first two unlock cycles are no more needed (see Table 14: Fast program commands (16-bit mode)).
34/95
M29DW127G
Table 12.
Command interface
Standard commands (16-bit mode)
Command(1)
Length
Bus operations(2)
1st
Add
2nd
Data Add Data
3rd
Add
4th
5th
6th
Data Add Data Add Data Add Data
1
X
F0
3
555
AA
2AA
55
X
F0
3
555
AA
2AA
55
(BKA)
555
90
(3)(4)
(3)(4)
Program (5)
4
555
AA
2AA
55
555
A0
PA
PD
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Block Erase
6+
555
AA
2AA
55
555
80
555
AA
2AA
55
BAd
30
Erase/Program Suspend
1
BKA
B0
Erase/Program Resume
1
BKA
30
Read CFI Query
1
BKA
(555)
98
Read/Reset
Manufacturer code
Device code
Extended memory
Auto
Select block protection
indicator
Block protection
status
1. The device doesn’t tolerate FFh as a valid command, and once FFh is issued to the device, the M29DW127G will enter
unexpected state. Adding a F0h command systematically after FFh command is necessary.
2. X don’t care, PA program address, PD program data, BAd any address in block, BKA bank address, values hexadecimal.
3. These cells represent read cycles. All the other cells are write cycles.
4. The auto select addresses and data are given in Table 7: Read electronic signature, auto select mode method (16-bit
mode), and Table 9: Block protection (16-bit mode), except for A9 that is ‘don’t care’.
5. In unlock bypass, the first two unlock cycles are no more needed (see Table 14: Fast program commands (16-bit mode)).
7.2
Fast program commands
The M29DW127G offers a set of fast program commands to improve the programming
throughput:
Write to Buffer Program
Enhanced Buffered Program
Unlock Bypass.
See Table 14: Fast program commands (16-bit mode) for a summary of the fast program
commands.
When VPPH is applied to the VPP/write protect pin the memory automatically enters unlock
bypass mode (see Section 7.2.6: Unlock Bypass command).
After programming has started, bus read operations in the memory output the status register
content (bus reading operations from banks different from those including the block being
programmed, output the memory array content). Write to Buffer Program command can be
35/95
Command interface
M29DW127G
suspended and then resumed by issuing a Program Suspend command and a Program
Resume command, respectively (see Section 7.1.8: Program Suspend command and
Section 7.1.9: Program Resume command).
After the fast program operation has completed, the memory will return to the read mode,
unless an error has occurred. When an error occurs bus read operations to the memory will
continue to output the status register. A Read/Reset command must be issued to reset the
error condition and return to read mode. One of the erase commands must be used to set all
the bits in a block or in the whole memory from ’0’ to ’1’.
Typical program times are given in Table 18: Program, erase times and program, erase
endurance cycles.
7.2.1
Write to Buffer Program command
The Write to Buffer Program command makes use of the device’s 32-word / 64 byte write
buffer to speed up programming. 32 words / 64 bytes can be loaded into the write buffer.
Each write buffer has the same A22-A5 addresses.The Write to Buffer Program command
dramatically reduces system programming time compared to the standard non-buffered
Program command.
When issuing a Write to Buffer Program command, the VPP/WP pin can be either held High,
VIH, or raised to VPPH.
See Table 18 for details on typical write to buffer program times in both cases.
The following successive steps are required to issue the Write to Buffer Program command:
1.
The Write to Buffer Program command starts with two unlock cycles
2.
The third bus write cycle sets up the Write to Buffer Program command. The setup
code can be addressed to any location within the targeted block
3.
The fourth bus write cycle sets up the number of words/bytes to be programmed. Value
N is written to the same block address, where N+1 is the number of words/bytes to be
programmed. N+1 must not exceed the size of the write buffer or the operation will
abort
4.
5.
The fifth cycle loads the first address and data to be programmed
Use N bus write cycles to load the address and data for each word/byte into the write
buffer. Addresses must lie within the range from the start address+1 to the start
address + N-1.
All the addresses used in the write to buffer program operation must lie within the same
page.
To program the content of the write buffer, this command must be followed by a Write to
Buffer Program Confirm command.
If an address is written several times during a write to buffer program operation, the
address/data counter will be decremented at each data load operation and the data will be
programmed to the last word loaded into the buffer.
Invalid address combinations or failing to follow the correct sequence of bus write cycles will
abort the Write to Buffer Program.
The status register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status
during a write to buffer program operation.
It is possible to detect program operation fails when changing programmed data from ‘0’ to
‘1’, that is when reprogramming data in a portion of memory already programmed.
36/95
M29DW127G
Command interface
See Appendix D, Figure 29: Write to buffer program flowchart and pseudocode, for a
suggested flowchart on using the Write to Buffer Program command.
7.2.2
Enhanced Buffered Program command
The Enhanced Buffered Program command makes use of the device’s 256-word write buffer
to speed up programming. 256 words can be loaded into the write buffer. Each write buffer
has the same A22-A8 addresses. The Enhanced Buffered Program command dramatically
reduces system programming time compared to both the standard non-buffered Program
command and the Write to Buffer command.
When issuing an Enhanced Buffered Program command, the VPP/WP pin can be either held
High, VIH, or raised to VPPH.
See Table 18: Program, erase times and program, erase endurance cycles for details on
typical enhanced buffered program times in both cases.
Three successive steps are required to issue the Enhanced Buffered Program command:
The Enhanced Buffered Program command starts with two unlock cycles
The third bus write cycle sets up the Enhanced Buffered Program command. The setup
code can be addressed to any location within the targeted block
The fourth bus write cycle loads the first address and data to be programmed. There a
total of 256 address and data loading cycles.
To program the content of the write buffer, the Enhanced Buffered Program command must
be followed by an Enhanced Buffered Program Confirm command. The command ends with
an internal enhanced buffered program confirm cycle.
Note that address/data cycles must be loaded in an increasing address order (from
ADD[7:0]=00000000 to ADD[7:0]=11111111) and completely (all 256 words). Invalid address
combinations or failing to follow the correct sequence of bus write cycles will abort the
enhanced buffered program.
The status register bits DQ1, DQ5, DQ6, and DQ7 can be used to monitor the device status
during an enhanced buffered program operation.
An external supply (12 V) can be used to improve programming efficiency.
It is possible to detect program operation fails when changing programmed data from ‘0’ to
‘1’, that is when reprogramming data in a portion of memory already programmed. The
resulting data will be the logical OR between the previous and the current value.
See Appendix D and Figure 30: Enhanced buffered program flowchart and pseudocode, for
a suggested flowchart on using the Enhanced Buffered Program command.
7.2.3
Buffered Program Abort and Reset command
A Buffered Program Abort and Reset command must be issued to abort the write to buffer
program and enhanced buffered program operation and reset the device in read mode.
37/95
Command interface
M29DW127G
The write to buffer and enhanced buffered programming sequence can be aborted in the
following ways:
Load a value that is greater than the page buffer size during the number of locations to
program step in the Write to Buffer Program command
Write to an address in a block different than the one specified during the write-bufferload command
Write an address/data pair to a different write-buffer-page than the one selected by the
starting address during the write buffer data loading stage of the operation
Write data other than the Confirm command after the specified number of data load
cycles
Load address/data pairs in an incorrect sequence during the enhanced buffered
program.
The abort condition is indicated by DQ1 = 1, DQ7 = DQ7 (for the last address location
loaded), DQ6 = toggle, and DQ5 = 0 (all of which are status register bits). A Buffered
Program Abort and Reset command sequence must be written to reset the device for the
next operation. Note that the full 3-cycle Buffered Program Abort and Reset command
sequence is required when using write to buffer and enhanced buffered programming
features in unlock bypass mode.
7.2.4
Write to Buffer Program Confirm command
The Write to Buffer Program Confirm command is used to confirm a Write to Buffer Program
command and to program the N+1 words/bytes loaded in the write buffer by this command.
7.2.5
Enhanced Buffered Program Confirm command
The Enhanced Buffered Program Confirm command is used to confirm an Enhanced
Buffered Program command and to program the 256 words loaded in the buffer.
7.2.6
Unlock Bypass command
The Unlock Bypass command is used to place the device in unlock bypass mode. When the
device enters the unlock bypass mode, the two initial unlock cycles required in the standard
program command sequence are no more needed, and only two write cycles are required to
program data, instead of the normal four cycles (see Note 5 below Table 12: Standard
commands (16-bit mode)). This results in a faster total programming time.
Unlock Bypass command is consequently used in conjunction with the Unlock Bypass
Program command to program the memory faster than with the standard program
commands. When the cycle time to the device is long, considerable time saving can be
made by using these commands. Three bus write operations are required to issue the
Unlock Bypass command.
38/95
M29DW127G
Command interface
When in unlock bypass mode, only the following commands are valid:
The Unlock Bypass Program command can be issued to program addresses within the
memory
The Unlock Bypass Block Erase command can then be issued to erase one or more
memory blocks
The Unlock Bypass Chip Erase command can be issued to erase the whole memory
array
The Unlock Bypass Write to Buffer Program command can be issued to speed up
programming operation
The Unlock Bypass Enhanced Buffered Program command can be issued to speed up
programming operation
The Unlock Bypass CFI command can be issued to read the CFI when the memory is
in the unlock bypass mode
The Unlock Bypass Reset command can be issued to return the memory to read mode.
In unlock bypass mode the memory can be read as if in read mode.
7.2.7
Unlock Bypass Program command
The Unlock Bypass Program command can be used to program one address in the memory
array at a time. The command requires two bus write operations, the final write operation
latches the address and data and starts the program/erase controller.
The program operation using the Unlock Bypass Program command behaves identically to
the program operation using the Program command. The operation cannot be aborted, a
bus read operation to the memory outputs the status register (bus reading operations from a
bank different from the one including the block being programmed, output the memory array
content). See the Program command for details on the behavior.
7.2.8
Unlock Bypass Block Erase command
The Unlock Bypass Block Erase command can be used to erase one or more memory
blocks at a time. The command requires two bus write operations instead of six using the
standard Block Erase command. The final bus write operation latches the address of the
block and starts the program/erase controller.
To erase multiple block (after the first two bus write operations have selected the first block
in the list), each additional block in the list can be selected by repeating the second bus
write operation using the address of the additional block.
The Unlock Bypass Block Erase command behaves in the same way as the Block Erase
command: the operation cannot be aborted, and a bus read operation to the memory
outputs the status register (bus reading operations from banks different from those including
the blocks being erased, output the memory array content). See Section 7.1.5: Block Erase
command for details.
7.2.9
Unlock Bypass Chip Erase command
The Unlock Bypass Chip Erase command can be used to erase all memory blocks at a time.
The command requires two bus write operations only instead of six using the standard Chip
Erase command. The final bus write operation starts the program/erase controller.
39/95
Command interface
M29DW127G
The Unlock Bypass Chip Erase command behaves in the same way as the Chip Erase
command: the operation cannot be aborted, and a bus read operation to the memory
outputs the status register (see Section 7.1.4: Chip Erase command for details).
7.2.10
Unlock Bypass Write to Buffer Program command
The Unlock Bypass Write to Buffer command can be used to program the memory in fast
program mode. The command requires two bus write operations less than the standard
Write to Buffer Program command.
The Unlock Bypass Write to Buffer Program command behaves in the same way as the
Write to Buffer Program command: the operation cannot be aborted and a bus read
operation to the memory outputs the status register (bus reading operations from a bank
different from the one including the block being programmed, output the memory array
content). See Section 7.2.1: Write to Buffer Program command for details.
The Write to Buffer Program Confirm command is used to confirm an Unlock Bypass Write
to Buffer Program command and to program the N+1 words/bytes loaded in the write buffer
by this command.
7.2.11
Unlock Bypass Enhanced Buffered Program command
The Unlock Bypass Enhanced Buffered Program command can be used to program the
memory in fast program mode. The command requires two address/data loading cycles less
than the standard Enhanced Buffered Program command (see Table 15: Enhanced buffered
program commands).
The Unlock Bypass Enhanced Buffered Program command behaves identically to the
enhanced buffered program operation using the Enhanced Buffered Program command.
The operation cannot be aborted and a bus read operation to the memory outputs the status
register (bus reading operations from a bank different from the one including the block being
programmed, output the memory array content). See Section 7.2.2: Enhanced Buffered
Program command for details on the behavior.
The Enhanced Buffered Program Confirm command is used to confirm an Unlock Bypass
Enhanced Buffered Program command and to program the 256 words loaded in the buffer.
7.2.12
Unlock Bypass CFI command
The Unlock Bypass CFI command allows to use any address in the bank to perform a CFI
query when the memory is in the unlock bypass mode.
7.2.13
Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to read/reset mode from unlock
bypass mode. Two bus write operations are required to issue the Unlock Bypass Reset
command. Read/Reset command does not exit from unlock bypass mode.
40/95
M29DW127G
Table 13.
Command interface
Fast program commands (8-bit mode)
Command
Write to Buffer
Program
Length
Bus write operations(1)
N+5
Write to Buffer
Program Confirm
1
Buffered
Program Abort
and Reset
1st
2nd
3rd
4th
5th
6th
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
AAA
AA
555
55
BAd
25
BAd
N(2)
PA(3)
PD
WBL(4)
PD
BAd
(5)
29
3
AAA
AA
555
55
AAA
F0
Unlock Bypass
3
AAA
AA
555
55
AAA
20
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass
Block Erase
2+
X
80
BAd
30
Unlock Bypass
Chip Erase
2
X
80
X
10
Unlock Bypass
Write to Buffer
Program
N+3
BAd
25
BAd
N(2)
PA(3)
PD
Unlock Bypass
CFI
1
BKA
98
Unlock Bypass
Reset
2
X
90
X
00
Add
Data
WBL
PD
(4)
1. X don’t care, PA program address, PD program data, BAd any address in the block, BKA bank address, WBL write buffer
location. All values in the table are in hexadecimal.
2. The maximum number of cycles in the command sequence is 36. N+1 is the number of words to be programmed during the
write to buffer program operation.
3. Each buffer has the same A22-A5 addresses. A0-A4 are used to select a word within the N+1 word page.
4. The 6th cycle has to be issued N time. WBL scans the word inside the page.
5. BAd must be identical to the address loaded during the write to buffer program 3rd and 4th cycles.
Table 14.
Fast program commands (16-bit mode)
Command
Write to Buffer
Program
Length
Bus write operations(1)
N+5
Write to Buffer
Program Confirm
1
Buffered Program
Abort and Reset
Unlock Bypass
1st
2nd
3rd
4th
5th
6th
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
555
AA
2AA
55
BAd
25
BAd
N(2)
PA(3)
PD
BAd
(5)
29
3
555
AA
2AA
55
555
F0
3
555
AA
2AA
55
555
20
Add
WBL
(4)
Data
PD
41/95
Command interface
Table 14.
M29DW127G
Fast program commands (16-bit mode)
Length
Bus write operations(1)
Command
1st
2nd
3rd
Add
Data
Add
Data
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass
Block Erase
2+
X
80
BAd
30
Unlock Bypass
Chip Erase
2
X
80
X
10
Unlock Bypass
Write to Buffer
Program
N+3
BAd
25
BAd
N(2)
Unlock Bypass
CFI
1
BKA
98
Unlock Bypass
Reset
2
X
90
X
00
Add
4th
Data
PA
Add
Data
WBL
PD
(3)
5th
(4)
Add
6th
Data
Add
Data
PD
1. X don’t care, PA program address, PD program data, BAd any address in the block, BKA bank address, WBL write buffer
location. All values in the table are in hexadecimal.
2. The maximum number of cycles in the command sequence is 36. N+1 is the number of words to be programmed during
the write to buffer program operation.
3. Each buffer has the same A22-A5 addresses. A0-A4 are used to select a word within the N+1 word page.
4. The 6th cycle has to be issued N time. WBL scans the word inside the page.
5. BAd must be identical to the address loaded during the write to buffer program 3rd and 4th cycles.
Enhanced buffered program commands(1)(2)
Table 15.
Command
Length
Bus write operations
1st
2nd
3rd
Add
Data
Add
Data
Add
2AA
55
BAd
BAd
(00)
Data
Enhanced
Buffered
Program
259
555
AA
Enhanced
Buffered
Program
Confirm
1
BAd
(00)
29
Unlock
Bypass
Enhanced
Buffered
Program
257
BAd
33
1. Only available from week 8 of 2008.
2. BAd any address in the block.
42/95
4th
...
257th
Data Add
Data
Add
Data
BAd
(00)
Data
...
...
33
Add
BAd
(FF)
Data
Data
258th
Add
Data
259th
Add
Data
BAd
(FF)
Data
260th
Add
Data
M29DW127G
7.3
Command interface
Protection commands
Blocks can be protected individually against accidental program, erase or read operations.
The device block protection scheme is shown in Figure 6: Software protection scheme. See
Table 17: Block protection commands (16-bit mode) for a summary of the block protection
commands.
The memory block and extended memory block protection is configured through the Lock
register (see Section 8.1: Lock register).
7.3.1
Enter Extended Memory Block command
The M29DW127G has one extra 256-word block (extended memory block) that can only be
accessed using the Enter Extended Memory Block command.
The extended memory block is divided in two memory areas of 128 words each: the first
one is factory locked and the second one is customer lockable.
Three Bus Write cycles are required to issue the Extended Memory Block command. Once
the command has been issued the device enters the extended memory block mode where
all bus read or program operations are conducted on the extended memory block. Once the
device is in the extended block mode, the extended memory block is addressed by using
the addresses occupied by the first boot block in the other operating modes (see Table 37:
Block addresses).
The device remains in extended memory block mode until the Exit Extended Memory Block
command is issued or power is removed from the device. After power-up or hardware reset,
the device reverts to read mode where the commands issued to the first boot block address
space will address the first boot block.
The extended memory block cannot be erased, and can be treated as one-time
programmable (OTP) memory.
In extended block mode only array cell locations (bank A) with the same addresses as the
extended block are not accessible. In extended block mode dual operations are allowed and
the extended block physically belongs to bank A. In extended block mode, Erase, Chip
Erase, Erase Suspend and Erase Resume commands are not allowed.
To exit from the extended memory block mode the Exit Extended Memory Block command
must be issued.
The extended memory block can be protected by setting the extended memory block
protection bit to ‘1’ (see Section 8.1: Lock register); however once protected the protection
cannot be undone.
Note:
When the device is in the extended memory block mode, the VPP/WP pin cannot be used
for fast programming and the unlock bypass mode is not available (see Section 2.8:
VPP/write protect (VPP/WP)).
7.3.2
Exit Extended Memory Block command
The Exit Extended Memory Block command is used to exit from the extended memory block
mode and return the device to read mode. Four bus write operations are required to issue
the command.
43/95
Command interface
7.3.3
M29DW127G
Lock register command set
The M29DW127G offers a set of commands to access the lock register and to configure
and verify its content. See the following sections in conjunction with Section 8.1: Lock
register and Table 17: Block protection commands (16-bit mode).
Enter Lock Register Command Set command
Three bus write cycles are required to issue the Enter Lock Register Command set
command. Once the command has been issued, all bus read or program operations are
issued to the lock register.
Lock Register Program and Lock Register Read command
The Lock Register Program command allows to configure the lock register. The
programmed data can then be checked by issuing a Lock Register Read command.
An Exit Protection Command set command must then be issued to return the device to read
mode (see Section 7.3.8: Exit protection command set command).
7.3.4
Password protection mode command set
Enter Password Protection Command Set command
Three bus write cycles are required to issue the Enter Password Protection Command Set
command. Once the command has been issued, the commands related to the password
protection mode can be issued to the device.
Password Program command
The Password Program command is used to program the 64-bit password used in the
password protection mode.
To program the 64-bit password, the complete command sequence must be entered four
times at four consecutive addresses selected by A1-A0.
The password can be checked by issuing a Password Read command.
Once password program operation has completed, an Exit Protection Command Set
command must be issued to return the device to read mode. The password protection mode
can then be selected.
By default, all password bits are set to ‘1’.
Password Read command
The Password Read command is used to verify the password used in password protection
mode.
To verify the 64-bit password, the complete command sequence must be entered four times
at four consecutive addresses selected by A1-A0.
If the password mode lock bit is programmed and the user attempts to read the password,
the device will output FFh onto the I/O data bus.
An Exit Protection Command Set command must be issued to return the device to read
mode.
44/95
M29DW127G
Command interface
Password Unlock command
The Password Unlock command is used to clear the NVPB lock bit allowing to modify the
NVPBs.
The Password Unlock command must be issued along with the correct password.
There must be a 1 μs delay between successive password unlock commands in order to
prevent hackers from cracking the password by trying all possible 64-bit combinations. If
this delay is not respected, the latest command will be ignored.
Approximately 1 μs is required for unlocking the device after the valid 64-bit password has
been provided.
7.3.5
Non-volatile protection mode command set
Enter Non-volatile Protection Command Set command
Three bus write cycles are required to issue the Enter Non-volatile Protection Command Set
command. Once the command has been issued, the commands related to the non-volatile
protection mode can be issued to the device.
Non-volatile Protection Bit Program command (NVPB Program)
A block can be protected from program or erase by issuing a Non-volatile Protection Bit
command along with the block address. This command sets the NVPB to ‘1’ for a given
block.
Read Non-volatile Protection Bit Status command (Read NVPB Status)
The status of a NVPB for a given block or group of blocks can be read by issuing a Read
Non-Volatile Modify Protection Bit command along with the block address.
Clear all Non-volatile Protection Bits command (Clear all NVPBs)
The NVPBs are erased simultaneously by issuing a Clear all Non-volatile Protection Bits
command. No specific block address is required. If the NVPB lock bit is set to ‘0’, the
command fails.
45/95
Command interface
Figure 7.
M29DW127G
NVPB program/erase algorithm
Enter NVPB
command set.
Program NVPB
Addr = BAd
Read Byte twice
Addr = BAd
DQ6=
Toggle
NO
YES
NO
DQ5=1
Wait 500 μs
YES
Read Byte twice
Addr = BAd
DQ6=
Toggle
NO
Read Byte twice
Addr = BAd
NO
DQ0=
'1'(Erase)
'0'(Program)
YES
Fail
Reset
Pass
Exit NVPB
command set
AI14242
46/95
M29DW127G
7.3.6
Command interface
NVPB lock bit command set
Enter NVPB Lock Bit Command Set command
Three bus write cycles are required to issue the Enter NVPB Lock Bit Command Set
command. Once the command has been issued, the commands allowing to set the NVPB
lock bit can be issued to the device.
NVPB Lock Bit Program command
This command is used to set the NVPB Lock bit to ‘0’ thus locking the NVPBs, and
preventing them from being modified.
Read NVPB Lock Bit Status command
This command is used to read the status of the NVPB lock bit.
7.3.7
Volatile protection mode command set
Enter Volatile Protection Command Set command
Three bus write cycles are required to issue the Enter Volatile Protection Command Set
command. Once the command has been issued, the commands related to the volatile
protection mode can be issued to the device.
Volatile Protection Bit Program command (VPB Program)
The VPB Program command individually sets a VPB to ‘0’ for a given block.
If the NVPB for the same block is set, the block is locked regardless of the value of the VPB
bit (see Table 20: Block protection status).
Read VPB Status command
The status of a VPB for a given block can be read by issuing a Read VPB Status command
along with the block address.
VPB Clear command
The VPB Clear command individually clears (sets to ‘1’) the VPB for a given block.
If the NVPB for the same block is set, the block is locked regardless of the value of the VPB
bit. (see Table 20: Block protection status).
7.3.8
Exit protection command set command
The Exit Protection Command Set command is used to exit from the Lock register,
password protection, non-volatile protection, volatile protection, and NVPB lock bit
command set mode. It returns the device to read mode.
47/95
Command interface
Table 16.
M29DW127G
Block protection commands (8-bit mode)(1)(2)(3)
Length
Bus operations
Extended block sector
Volatile protection
NVPB lock bit
Non-volatile protection
Password protection
Lock register
Command
2nd
3rd
4th
Ad
Data
Ad
Data
Ad
Data
AAA
40
AAA
60
Ad
Data
Enter Lock Register
Command Set (4)
3
AAA
AA
555
55
Lock Register Program
2
X
A0
00
DATA(5)
Lock Register Read
1
X
DATA(5)
Enter Password Protection
Command Set (4)
3
AAA
AA
555
55
2
X
A0
PWAn
PWDn
4
00
PWD0
01
PWD1
02
PWD2
03
PWD3
7
00
25
00
03
00
PWD0
01
PWD1
Enter Non-volatile Protection
Command Set (4)
3
AAA
AA
555
55
(BKA)
AAA
C0
NVPB Program(8)
2
X
A0
(BKA)
BAd
00
Clear all NVPBs(9)
2
X
80
00
30
Read NVPB Status
1
(BKA)
BAd
RD(0)
Enter NVPB Lock Bit
Command Set
3
AAA
AA
555
55
AAA
50
NVPB Lock Bit Program
2
X
A0
X
00
Read NVPB Lock Bit Status
1
BKA
RD(0)
Enter Volatile Protection
Command Set
3
AAA
AA
555
55
(BKA)
AAA
E0
VPB Program
2
X
A0
(BKA)
BAd
00
Read VPB Status
1
(BKA)
BAd
RD(0)
VPB Clear
2
X
A0
(BKA)
BAd
01
3
AAA
AA
555
55
AAA
88
AAA
90
X
00
Password Program
(6)(7)
Password Read
Password Unlock
(7)
Enter Extended Block
(4)
2
X
A0
Extended Block Read (4)
1
Ad
DATA(5)
Exit Extended Block
4
AAA
2
X
Extended Block Program
Exit Protection Command Set(10)
1.
1st
PA
DATA
AA
555
55
90
X
00
5th
6th
Ad
Data
Ad
Data
02
PWD2
03
PWD3
7th
Ad Data
00
(5)
PA program address, Ad address, BAd any address in the block, BKA bank address, RD read data, PWDn password word (n = 0 to 3), PWAn password address (n
= 0 to 3), X don’t care. All values in the table are in hexadecimal.
2.
Grey cells represent read cycles. The other cells are write cycles.
3.
DQ15 to DQ8 are ‘don’t care’ during unlock and command cycles. A22 to A16 are ‘don’t care’ during unlock and command cycles unless an address is required.
4.
An enter command sequence must be issued prior to any operation. It disables read and write operations from and to block 0. Read and write operations from any
other block are allowed.
5.
DATA = Extended block content.
6.
Only one portion of password can be programmed or read by each Password Program command.
7.
The password portion can be entered or read in any order as long as the entire 64-bit password is entered or read.
8.
Protected and unprotected states correspond to 00 and 01, respectively.
9.
The Clear all NVPBs command programs all NVPBs before erasure in order to prevent the over-erasure of previously cleared non-volatile modify protection bits.
10. If an Entry Command Set command is issued, an Exit Protection Command Set command must be issued to return the device to read mode.
48/95
29
M29DW127G
Table 17.
Command interface
Block protection commands (16-bit mode)(1)(2)(3)
Length
Bus operations
Extended block sector
Volatile protection
NVPB lock bit
Non-volatile protection
Password protection
Lock register
Command
2nd
3rd
4th
Ad
Data
Ad
Data
Ad
Data
555
40
555
60
Ad
Data
Enter Lock Register
Command Set(4)
3
555
AA
2AA
55
Lock Register Program
2
X
A0
00
DATA(5)
Lock Register Read
1
X
DATA(5)
Enter Password Protection
Command Set(4)
3
555
AA
2AA
55
2
X
A0
PWAn
PWDn
4
00
PWD0
01
PWD1
02
PWD2
03
PWD3
7
00
25
00
03
00
PWD0
01
PWD1
Enter Non-volatile Protection
Command Set(4)
3
555
AA
2AA
55
(BKA)
555
C0
NVPB Program(8)
2
X
A0
(BKA)
BAd
00
Clear all NVPBs(9)
2
X
80
00
30
Read NVPB Status
1
(BKA)
BAd
RD(0)
Enter NVPB Lock Bit
Command Set
3
555
AA
2AA
55
555
50
NVPB Lock Bit Program
2
X
A0
X
00
Read NVPB Lock Bit Status
1
BKA
RD(0)
Enter Volatile Protection
Command Set
3
555
AA
2AA
55
(BKA)
555
E0
VPB Program
2
X
A0
(BKA)
BAd
00
Read VPB Status
1
(BKA)
BAd
RD(0)
VPB Clear
2
X
A0
(BKA)
BAd
01
3
555
AA
2AA
55
555
88
555
90
X
00
Password Program
(6)(7)
Password Read
Password Unlock
(7)
Enter Extended Block
(4)
2
X
A0
Extended Block Read (4)
1
Ad
DATA(5)
Exit Extended Block
4
555
AA
2AA
55
2
X
90
X
00
Extended Block Program
Exit Protection Command Set(10)
1.
1st
PA
DATA
5th
6th
Ad
Data
Ad
Data
02
PWD2
03
PWD3
7th
Ad Data
00
29
(5)
PA program address, Ad address, BAd any address in the block, BKA bank address, RD read data, PWDn password word (n = 0 to 3), PWAn password address (n
= 0 to 3), X don’t care. All values in the table are in hexadecimal.
2.
Grey cells represent read cycles. The other cells are write cycles.
3.
DQ15 to DQ8 are ‘don’t care’ during unlock and command cycles. A22 to A16 are ‘don’t care’ during unlock and command cycles unless an address is required.
4.
An enter command sequence must be issued prior to any operation. It disables read and write operations from and to block 0. Read and write operations from any
other block are allowed.
5.
DATA = Extended block content.
6.
Only one portion of password can be programmed or read by each Password Program command.
7.
The password portion can be entered or read in any order as long as the entire 64-bit password is entered or read.
8.
Protected and unprotected states correspond to 00 and 01, respectively.
9.
The Clear all NVPBs command programs all NVPBs before erasure in order to prevent the over-erasure of previously cleared non-volatile modify protection bits.
10. If an Entry Command Set command is issued, an Exit Protection Command Set command must be issued to return the device to read mode.
49/95
Command interface
Table 18.
M29DW127G
Program, erase times and program, erase endurance cycles
Parameter
Min
Typ(1)(2)
Max(2)
Unit
40
400(3)
s
Chip Erase
Block Erase (128 Kwords/256
Kbytes)(4)
1
Erase Suspend latency time
25
Block Erase timeout
μs
μs
16
Write to Buffer Program
(64 bytes at-a-time)
VPP /WP = VPPH
51
VPP /WP = VIH
78
Single Word Program
Word Program
35
50
Single Byte Program
Byte Program
s
μs
200
(3)
μs
16
Write to Buffer Program
(32 words at-a-time)
VPP /WP = VPPH
51
VPP /WP = VIH
78
μs
200(3)
μs
270
800(3)
s
Chip Program (word by word)
135
400(3)
s
Chip Program (Write to Buffer Program)(5)
20
200(3)
s
Chip Program (byte by byte)
Chip Program (Write to Buffer Program with VPP /WP = VPPH)
Chip Program (Enhanced Buffered Program)
(5)
13
(5)
(3)
50
s
8
40
s
Chip Program (Enhanced Buffered Program with VPP /WP = VPP )
5
25
s
Program Suspend latency time
5
15
μs
(5)
Program/Erase cycles (per block)
Data retention
100,000
Cycles
20
Years
1. Typical values measured at room temperature and nominal voltages and for not cycled devices.
2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and V CC after 100,000 program/erase cycles.
4. Block Erase polling cycle time (seeFigure 26: Data polling AC waveforms).
5. Intrinsic program timing, that means without the time required to execute the bus cycles to load the program commands.
50/95
M29DW127G
8
Registers
Registers
The device feature two registers:
8.1
A lock register that allows to configure the memory blocks and extended memory block
protection (see Table 20: Block protection status)
A status register that provides information on the current or previous program or erase
operations.
Lock register
The lock register is a 16-bit one-time programmable register. The bits in the lock register are
summarized in Table 19: Lock register bits.
See Section 7.3.3: Lock register command set for a description of the commands allowing
to read and program the lock register.
8.1.1
Volatile lock boot bit (DQ4)
DQ4 sets the default values for volatile block protection: when programmed, the blocks are
protected at power-up.
8.1.2
Password protection mode lock bit (DQ2)
The password protection mode lock bit, DQ2, is one-time programmable. Programming
(setting to ‘0’) this bit permanently places the device in password protection mode.
Any attempt to program the password protection mode lock bit when the non-volatile
protection mode bit is programmed causes the operation to abort and the device to return to
read mode.
8.1.3
Non-volatile protection mode lock bit (DQ1)
The non-volatile protection mode lock bit, DQ1, is one-time programmable. Programming
(setting to ‘0’) this bit permanently places the device in non-volatile protection mode.
When shipped from the factory, all parts default to operate in non-volatile protection mode.
The memory blocks can be either unprotected (NVPBs set to ‘1’) or protected (NVPBs set to
‘0’), according to the ordering option that has been chosen.
Any attempt to program the non-volatile protection mode lock bit when the password
protection mode bit is programmed causes the operation to abort and the device to return to
read mode.
8.1.4
Extended block protection bit (DQ0)
If the device has not been shipped with the extended memory block factory locked, the
block can be protected by setting the extended memory block protection bit, DQ0, to ‘0’.
However, this bit is one-time programmable and once protected the extended memory block
cannot be unprotected.
The extended memory block protection status can be read in auto select mode by issuing
an Auto Select command (see Table 12: Standard commands (16-bit mode)).
51/95
Registers
8.1.5
M29DW127G
DQ15 to DQ5 and DQ3 reserved
They are ‘don’t care’.
Table 19.
Lock register bits(1)
DQ15-5
DQ4
DQ3
DQ2
DQ1
DQ0
Don’t care
Volatile lock
boot bit
Don’t care
Password protection
mode lock bit
Non-volatile protection
mode lock bit
Extended block
protection bit
1. DQ0, DQ1, DQ2 and DQ4 are set to ‘1’ when shipped from the factory.
Table 20.
Block protection status
NVPB lock
bit(1)
Block
NVPB(2)
Block
VPB(3)
Block protection
status
Block protection status
0
0
x
01h
Block protected (non-volatile protection through NVPB)
0
1
1
00h
Block unprotected
0
1
0
00h
Block protected (volatile protection through VPB)
1
0
x
01h
Block protected (non-volatile protection through NVPB)
1
1
0
01h
Block protected (volatile protection through VPB)
1
1
1
00h
Block unprotected
1. If the NVPB lock bit is set to ‘0’, all NVPBs are locked. If the NVPB lock bit is set to ‘1’, all NVPBs are unlocked.
2. If the block NVPB is set to ‘0’, the block is protected, if set to ‘1’, it is unprotected.
3. If the block VPB is set to ‘0’, the block is protected, if set to ‘1’, it is unprotected.
52/95
M29DW127G
Figure 8.
Registers
Lock register program flowchart
START
Write Unlock cycles:
Add 555h, Data AAh
Add 2AAh, Data 55h
Unlock cycle 1
unlock cycle 2
Write
Enter Lock Register command set:
Add 555h, Data 40h
Program Lock Register Data:
Add Dont' care, Data A0h
Add Dont' care(1), Data PDh
Polling algorithm
YES
Done
NO
DQ5 = 1
NO
YES
Device returned
to Read mode
PASS:
Write Lock Register Exit command:
Add Dont' care, Data 90h
Add Dont' care, Data 00h
FAIL
Reset to return
the device to Read mode
ai13677
1. PD is the programmed data (see Table 19: Lock register bits).
2. The lock register can only be programmed once.
53/95
Registers
8.2
M29DW127G
Status register
The M29DW127G has one status register. The various bits convey information and errors
on the current and previous program/erase operation. Bus read operations from any
address within the memory, always read the status register during program and erase
operations. It is also read during erase suspend when an address within a block being
erased is accessed.
The bits in the status register are summarized in Table 21: Status register bits.
8.2.1
Data polling bit (DQ7)
The data polling bit can be used to identify whether the program/erase controller has
successfully completed its operation or if it has responded to an erase suspend. The data
polling bit is output on DQ7 when the status register is read.
During program operations the data polling bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the program operation the memory
returns to read mode and bus read operations, from the address just programmed, output
DQ7, not its complement.
During erase operations the data polling bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the erase operation the memory returns to read
mode.
In erase suspend mode the data polling bit will output a ’1’ during a bus read operation
within a block being erased. The data polling bit will change from ’0’ to ’1’ when the
program/erase controller has suspended the erase operation.
Figure 9: Data polling flowchart, gives an example of how to use the data polling bit. A valid
address is the address being programmed or an address within the block being erased.
8.2.2
Toggle bit (DQ6)
The toggle bit can be used to identify whether the program/erase controller has successfully
completed its operation or if it has responded to an erase suspend. The toggle bit is output
on DQ6 when the status register is read.
During a program/erase operation the toggle bit changes from ’0’ to ’1’ to ’0’, etc., with
successive bus read operations at any address. After successful completion of the
operation the memory returns to read mode.
During erase suspend mode the toggle bit will output when addressing a cell within a block
being erased. The toggle bit will stop toggling when the program/erase controller has
suspended the erase operation.
Figure 10: Data toggle flowchart, gives an example of how to use the data toggle bit.
8.2.3
Error bit (DQ5)
The error bit can be used to identify errors detected by the program/erase controller. The
error bit is set to ’1’ when a program, block erase or chip erase operation fails to write the
correct data to the memory. If the error bit is set a Read/Reset command must be issued
54/95
M29DW127G
Registers
before other commands are issued. The error bit is output on DQ5 when the status register
is read.
Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to
do so will set DQ5 to ‘1’. A bus read operation to that address will show the bit is still ‘0’. One
of the erase commands must be used to set all the bits in a block or in the whole memory
from ’0’ to ’1’.
8.2.4
Erase timer bit (DQ3)
The erase timer bit can be used to identify the start of program/erase controller operation
during a Block Erase command. Once the program/erase controller starts erasing the erase
timer bit is set to ’1’. Before the program/erase controller starts the erase timer bit is set to ’0’
and additional blocks to be erased may be written to the command interface. The erase
timer bit is output on DQ3 when the status register is read.
8.2.5
Alternative toggle bit (DQ2)
The alternative toggle bit can be used to monitor the program/erase controller during erase
operations. The alternative toggle bit is output on DQ2 when the status register is read.
During chip erase and block erase operations the toggle bit changes from ’0’ to ’1’ to ’0’,
etc., with successive bus read operations from addresses within the blocks being erased. A
protected block is treated the same as a block not being erased. Once the operation
completes the memory returns to read mode.
During erase suspend the alternative toggle bit changes from ’0’ to ’1’ to ’0’, etc. with
successive bus read operations from addresses within the blocks being erased. Bus read
operations to addresses within blocks not being erased will output the memory array data as
if in read mode.
After an erase operation that causes the error bit to be set, the alternative toggle bit can be
used to identify which block or blocks have caused the error. The alternative toggle bit
changes from ’0’ to ’1’ to ’0’, etc. with successive bus read operations from addresses within
blocks that have not erased correctly. The alternative toggle bit does not change if the
addressed block has erased correctly.
8.3
Buffered program abort bit (DQ1)
The Buffered program abort bit, DQ1, is set to ‘1’ when a write to buffer program or
enhanced buffered program operation aborts. The Buffered Program Abort and Reset
command must be issued to return the device to read mode (see write to buffer program in
Section 7.1: Standard commands).
55/95
Registers
M29DW127G
Status register bits(1)
Table 21.
Operation
Address
Program(2)
DQ7
DQ6
DQ5 DQ3
DQ2
DQ1
RB
Bank address DQ7
Toggle
0
–
–
0
0
Program During Erase Suspend Bank address DQ7
Toggle
0
–
–
–
0
(2)
Buffered Program Abort
Bank address DQ7
Toggle
0
–
–
1
0
Program Error
Bank address DQ7
Toggle
1
–
–
–
Hi-Z
Chip Erase
Any address
0
Toggle
0
1
Toggle
–
0
Erasing block
0
Toggle
0
0
Toggle
–
0
Non-erasing
block
0
Toggle
0
0
No
toggle
–
0
Erasing block
0
Toggle
0
1
Toggle
–
0
Non-erasing
block
0
Toggle
0
1
No
toggle
–
0
Erasing block
1
No
Toggle
0
–
Toggle
–
Hi-Z
–
Hi-Z
Block Erase before timeout
Block Erase
Erase Suspend
Erase Error
Non-erasing
block
Data read as normal
Good block
address
0
Toggle
1
1
No
toggle
–
Hi-Z
Faulty block
address
0
Toggle
1
1
Toggle
–
Hi-Z
1. Unspecified data bits should be ignored.
2. DQ7 for write to buffer program and enhanced buffered program is related to the last address location
loaded.
56/95
M29DW127G
Figure 9.
Registers
Data polling flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
NO
DQ5 = 1
YES
READ DQ7
at VALID ADDRESS
DQ7
=
DATA
NO
FAIL
YES
PASS
AI07760
57/95
Registers
M29DW127G
Figure 10. Data toggle flowchart
START
READ DQ6
ADDRESS = BKA
READ
DQ5 & DQ6
ADDRESS = BKA
DQ6
=
TOGGLE
NO
YES
NO
DQ5
=1
YES
READ DQ6
TWICE
ADDRESS = BKA
DQ6
=
TOGGLE
NO
YES
FAIL
PASS
AI08929c
1. BKA=bank address being programmed or erased.
58/95
M29DW127G
9
Dual operations and multiple bank architecture
Dual operations and multiple bank architecture
The multiple bank architecture of the M29DW127G gives greater flexibility for software
developers to split the code and data spaces within the memory array. The dual operations
feature simplifies the software management of the device by allowing code to be executed
from one bank while another bank is being programmed or erased.
The dual operations feature means that while programming or erasing in one bank, read
operations are possible in another bank with zero latency.
Only one bank at a time is allowed to be in program or erase mode. However, certain
commands can cross bank boundaries, which means that during an operation only the
banks that are not concerned with the cross bank operation are available for dual
operations. For example, if a Block Erase command is issued to erase blocks in both bank A
and bank B, then only banks C or D are available for read operations while the erase is
being executed.
If a read operation is required in a bank, which is programming or erasing, the program or
erase operation can be suspended.
Also if the suspended operation was erase then a program command can be issued to
another block, so the device can have one block in erase suspend mode, one programming
and other banks in read mode.
By using a combination of these features, read operations are possible at any moment.
Table 22 and Table 23 show the dual operations possible in other banks and in the same
bank. Note that only the commonly used commands are represented in these tables.
Table 22.
Dual operations allowed in other banks(1)
Commands allowed in another bank
Status of bank
Read
Read
Status
Register
(2)
Read
CFI
Query
Select
Auto
Program
Erase
Program/Erase Program/Erase
Suspend
Resume
Idle
Yes
Yes(3)
Yes
Yes
Yes
Yes
Yes(3)
Yes(4)
Programming
Yes
No
No
No
–
–
No
No
Erasing
Yes
No
No
No
–
–
No
No
Program
suspended
Yes
No
Yes
Yes
No
No
–
No
Erase
suspended
Yes
No
Yes
Yes
Yes
No
–
Yes(5)
1. If several banks are involved in a program or erase operation, then only the banks that are not concerned with the
operation are available for dual operations.
2. Read Status Register is not a command. The status register can be read during a block program or erase operation.
3. Only after a program or erase operation in that bank.
4. Only after a Program or Erase Suspend command in that bank.
5. Only an erase resume is allowed if the bank was previously in erase suspend mode.
59/95
Dual operations and multiple bank architecture
Table 23.
M29DW127G
Dual operations allowed in same bank
Commands allowed in another bank
Status of
bank
Read
Read
Status
Register
Auto
Read CFI
Query
Select
(1)
Program
Erase
Program/
Program/Erase
Erase
Resume
Suspend
Idle
Yes
Yes
Yes
Yes
Yes
Yes
Yes(2)
Yes(3)
Programming
No
Yes
No
No
–
–
Yes(4)
–
–
Erasing
No
Yes
No
No
–
No
Yes(5)
Program
suspended
Yes
No
Yes
Yes
No
–
–
Yes
Erase
suspended
Yes(6)
Yes(7)
Yes
Yes
Yes(6)
No
–
Yes
1. Read status register is not a command. The status register can be read during a block program or erase operation.
2. Only after a program or erase operation in that bank.
3. Only after a Program or Erase Suspend command in that bank.
4. Only a program suspend.
5. Only an erase suspend.
6. Not allowed in the block or word that is being erased or programmed.
7. The status register can be read by addressing the block being erase suspended.
60/95
M29DW127G
10
Maximum ratings
Maximum ratings
Stressing the device above the rating listed in Table 24: Absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
operating sections of this specification is not implied.
Table 24.
Absolute maximum ratings
Symbol
Parameter
Min
Max
Unit
TBIAS
Temperature under bias
−50
125
°C
TSTG
Storage temperature
−65
150
°C
VIO
Input or output voltage (1)(2)
−0.6
VCC + 0.6
V
VCC
Supply voltage
−0.6
4
V
VCCQ
Input/output supply voltage
−0.6
4
V
Identification voltage
−0.6
10.5
V
Program voltage
−0.6
10.5
V
VID
VPPH(3)
1. Minimum voltage may undershoot to −2 V during transition and for less than 20 ns during transitions.
2. Maximum voltage may overshoot to VCC + 2 V during transition and for less than 20 ns during transitions.
3. VPPH must not remain at 9 V for more than a total of 80 hrs.
61/95
DC and AC parameters
11
M29DW127G
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 25: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 25.
Operating and AC measurement conditions
M29DW127G
Parameter
70 or 60 ns
80 ns
Min
Max
Min
Max
VCC supply voltage
2.7
3.6
2.7
3.6
V
VCCQ supply voltage (VCCQ ≤ VCC )
2.7
3.6
1.65
3.6
V
Ambient operating temperature
− 40
85
− 40
85
°C
Load capacitance (CL)
30
Input rise and fall times
30
10
Input pulse voltages
Input and output timing ref. voltages
VPP
ns
0 to VCCQ
0 to VCCQ
V
VCCQ/2
VCCQ/2
V
VCC
VCCQ
25 kΩ
DEVICE
UNDER
TEST
25 kΩ
CL
0.1 µF
pF
10
Figure 11. AC measurement load circuit
0.1 µF
CL includes JIG capacitance
AI05558b
Figure 12. AC measurement I/O waveform
VCCQ
VCCQ/2
0V
AI05557b
62/95
Unit
M29DW127G
Table 26.
DC and AC parameters
Power-up waiting timings
M29DW127G
Symbol
Parameter
Unit
70 or 60 ns
tVCHEL
VCC(1) High to Chip Enable Low
(1)
High to Chip Enable Low
80 ns
Min
55
μs
Min
55
μs
tVCQHEL
VCCQ
tVCHWL
VCC High to Write Enable Low
Min
500
μs
tVCQHWL
VCCQ High to Write Enable Low
Min
500
μs
1. VCC and VCCQ ramps must be synchronized during power-up.
Figure 13. Power-up waiting timings
tVCHEL
VCC
VCCQ
tVCQHEL
E
W
tVCHWL
tVCQHWL
AI14247
63/95
DC and AC parameters
M29DW127G
Device capacitance(1)
Table 27.
Symbol
CIN
Parameter
Input capacitance
Output capacitance
COUT
Test condition
Min
Max
Unit
VIN = 0 V
6
pF
VOUT = 0 V
12
pF
1. Sampled only, not 100% tested.
Table 28.
DC characteristics
Symbol
Parameter
Max
Unit
0 V ≤ VIN ≤ VCC
±1
μA
0 V ≤ VOUT ≤ VCC
±1
μA
Random read
E = VIL, G = VIH,
f = 6 MHz
10
mA
Page read
E = VIL, G = VIH,
f = 10 MHz
15
mA
E = VCCQ ± 0.2 V,
RP = VCCQ ± 0.2 V
100
μA
VPP /WP =
VIL or VIH
20
mA
VPP/WP = VPPH
20
mA
5
μA
ILI(1)
Input leakage current
ILO
Output leakage current
ICC1
ICC2
ICC3(2)
Read current
Supply current (standby)
Supply current (program/erase)
IPP1
IPP2
IPP3
Program
current
(Program)
Read or
standby
Reset
Test condition
Program/Erase
controller active
Min
VPP /WP ≤ VCC
Typ
1
RP = VSS ± 0.2 V
1
5
μA
Program
operation
ongoing
VPP /WP = 12 V ± 5%
1
10
mA
VPP/WP = VCC
1
5
μA
Erase
operation
ongoing
VPP /WP = 12 V ± 5%
3
10
mA
VPP/WP = VCC
1
5
μA
IPP4
Program
current (Erase)
VIL
Input Low voltage
VCC ≥ 2.7 V
−0.5
0.3V CCQ
V
VIH
Input High voltage
VCC ≥ 2.7 V
0.7VCCQ
VCCQ+0.4
V
VOL
Output Low voltage
IOL = 100 μA, VCC = VCC(min),
VCCQ = VCCQ(min)
0.15VCCQ
V
VOH
Output High voltage
IOH = 100 μA, VCC = VCC(min),
VCCQ = VCCQ(min)
VID
Identification voltage
8.5
9.5
V
Voltage for VPP/WP program
acceleration
8.5
9.5
V
Program/Erase lockout supply
voltage
1.8
2.5
V
VPPH
VLKO(2)
1. The maximum input leakage current is ±5 μA on the VPP /WP pin.
2. Sampled only, not 100% tested.
64/95
0.85VCCQ
V
M29DW127G
DC and AC parameters
Figure 14. Random read AC waveforms (8-bit mode)
VALID
A0-A22
tAVQV
VALID
tAXQX
E
tEHQZ
tGLQV
G
tGHQZ
tELQV
Hi-Z
DQ0-DQ14, DQ15A-1
Random_Read_AC-Wavefore-x8
Note:
BYTE = VIL
Figure 15. Random read AC waveforms (16-bit mode)
VALID
A–1,A0-A22
tAVQV
VALID
tAXQX
E
tGLQV
tEHQZ
G
tELQV
DQ0-DQ7
tGHQZ
Hi-Z
Random_Read_AC-Waveform-x16
Note:
BYTE = VIH
65/95
DC and AC parameters
M29DW127G
Figure 16. BYTE transition AC waveforms
A0-A22
VALID
A–1
VALID
tAXQX
tAVQV
BYTE
tBHQV
DATA OUT
DQ0-DQ7
tBLQX
Hi-Z
DQ8-DQ15
DATA OUT
tBLQZ
Byte_Transition_AC-Waveform
Note:
66/95
Chip Enable (E) and Output Enable (G) = VIL
DQ0-DQ15
G
E
tELQV
tAVQV
VALID
tGLQV
VALID
tAVQV1
VALID
A0-A2
VALID
VALID
A3-A22
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
tGHQZ
tGHQX
tEHQZ
VALID
VALID
AI08971d
tEHQX
M29DW127G
DC and AC parameters
Figure 17. Page read AC waveforms (8-bit mode)
67/95
68/95
DQ0-DQ15
DQ15A-1
G
E
tELQV
tAVQV
tGLQV
VALID
VALID
tAVQV1
VALID
A0-A2
VALID
VALID
A3-A22
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
tGHQZ
tGHQX
tEHQZ
VALID
VALID
AI08971c
tEHQX
DC and AC parameters
M29DW127G
Figure 18. Page read AC waveforms (16-bit mode)
M29DW127G
Table 29.
DC and AC parameters
Read AC characteristics
M29DW127G
Test
condition
80 ns
VCCQ=1.65 V to
VCC
Unit
70
80
ns
60
70
80
ns
E = VIL
Max
G = VIL
25
25
30
ns
Chip Enable Low to Output
Transition
G = VIL
Min
0
0
0
ns
Chip Enable Low to Output
Valid
G = VIL Max
60
70
80
ns
tOLZ
Output Enable Low to
Output Transition
E = VIL
Min
0
0
0
ns
tGLQV
tOE
Output Enable Low to
Output Valid
E = VIL Max
25
25
30
ns
tEHQZ(2)
tHZ
Chip Enable High to Output
Hi-Z
G = VIL Max
20
20
30
ns
tGHQZ(2)
tDF
Output Enable High to
Output Hi-Z
E = VIL Max
20
20
20
ns
tEHQX
tGHQX
tAXQX
tOH
Chip Enable, Output Enable
or Address Transition to
Output Transition
Min
0
0
0
ns
Symbol
Alt.
Parameter
tAVAV
tRC
Address Valid to Next
Address Valid
E = VIL
G = VIL
Min
60
tAVQV
tACC
Address Valid to Output
Valid
E = VIL
Max
G = VIL
tAVQV1
tPAGE
Address Valid to Output
Valid (Page)
tELQX(2)
tLZ
tELQV
tE
tGLQX(2)
70 ns
60 ns(1)
VCCQ=V CC VCCQ=VCC
tELBL
tELBH
tELFL Chip Enable to BYTE Low
tELFH or High
Max
5
5
5
ns
tBLQZ
tFLQZ BYTE Low to Output Hi-Z
Max
25
25
25
ns
tBHQV
tFHQV BYTE High to Output Valid
Max
30
30
30
ns
1. Only available upon customer request.
2. Sampled only, not 100% tested.
69/95
DC and AC parameters
M29DW127G
Figure 19. Write enable controlled program waveforms (8-bit mode)
3rd cycle
4th cycle
tAVAV
A0-A22/
A–1
Read cycle
Data Polling
tAVAV
555h
PA
PA
tAVWL
tWLAX
tELQV
tWHEH
tELWL
E
tGLQV
tGHWL
G
tWLWH
tWHWL
W
tDVWH
DQ0-DQ7
tWHWH1
AOh
PD
tGHQZ
DQ7 DOUT
tAXQX
DOUT
tWHDX
AI13333
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
of status register data polling bit and by a read operation that outputs the data, DOUT, programmed by the previous
Program command.
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 8.2.1: Data polling bit (DQ7)).
4. SeeTable 30: Write AC characteristics, write enable controlled, Table 31: Write AC characteristics, chip enable controlled
and Table 29: Read AC characteristics for details on the timings.
70/95
M29DW127G
DC and AC parameters
Figure 20. Write enable controlled program waveforms (16-bit mode)
3rd cycle
4th cycle
tAVAV
A0-A22
Read cycle
Data Polling
tAVAV
555h
PA
PA
tAVWL
tWLAX
tELQV
tWHEH
tELWL
E
tGLQV
tGHWL
G
tWLWH
tWHWL
W
tDVWH
DQ0-DQ1',
DQ15A–1
tWHWH1
AOh
PD
tGHQZ
DQ7 DOUT
tAXQX
DOUT
tWHDX
AI13699
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
of status register data polling bit and by a read operation that outputs the data, DOUT, programmed by the previous
Program command.
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 8.2.1: Data polling bit (DQ7)).
4. SeeTable 30: Write AC characteristics, write enable controlled, Table 31: Write AC characteristics, chip enable controlled
and Table 29: Read AC characteristics for details on the timings.
71/95
DC and AC parameters
Table 30.
M29DW127G
Write AC characteristics, write enable controlled
M29DW127G
Symbol
Alt
Parameter
Unit
60 ns(1)
70 ns
80 ns
tAVAV
tWC
Address Valid to Next Address Valid
Min
65
70
80
ns
tELWL
tCS
Chip Enable Low to Write Enable Low
Min
0
0
0
ns
tWLWH
tWP
Write Enable Low to Write Enable High
Min
35
35
35
ns
tDVWH
tDS
Input Valid to Write Enable High
Min
45
45
45
ns
tWHDX
tDH
Write Enable High to Input Transition
Min
0
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
0
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
Min
30
30
30
ns
tAVWL
tAS
Address Valid to Write Enable Low
Min
0
0
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
Min
45
45
45
ns
Output Enable High to Write Enable Low
Min
0
0
0
ns
tGHWL
tWHGL
tOEH
Write Enable High to Output Enable Low
Min
0
0
0
ns
tWHRL(2)
tBUSY
Program/Erase Valid to RB Low
Max
30
30
30
ns
tVCHEL
tVCS
VCC High to Chip Enable Low
Min
50
50
50
μs
1. Only available upon customer request.
2. Sampled only, not 100% tested.
72/95
M29DW127G
DC and AC parameters
Figure 21. Chip enable controlled program waveforms (8-bit mode)
3rd cycle
4th cycle
Data Polling
PA
PA
tAVAV
A0-A22/
A–1
555h
tAVEL
tELAX
tEHWH
tWLEL
W
tGHEL
G
tELEH
tEHEL1
E
tDVEH
DQ0-DQ7
tWHWH1
AOh
PD
DQ7 DOUT
tEHDX
AI13334
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
of status register data polling bit.
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 8.2.1: Data polling bit (DQ7)).
4. See Table 30: Write AC characteristics, write enable controlled, Table 31: Write AC characteristics, chip enable controlled
and Table 29: Read AC characteristics for details on the timings.
73/95
DC and AC parameters
M29DW127G
Figure 22. Chip enable controlled program waveforms (16-bit mode)
3rd cycle
4th cycle
Data Polling
PA
PA
tAVAV
A0-A22
555h
tAVEL
tELAX
tEHWH
tWLEL
W
tGHEL
G
tELEH
tEHEL1
E
tDVEH
DQ0-DQ14
A–1
tWHWH1
AOh
DQ7 DOUT
PD
tEHDX
AI14100
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
of status register data polling bit.
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 8.2.1: Data polling bit (DQ7)).
4. See Table 30: Write AC characteristics, write enable controlled, Table 31: Write AC characteristics, chip enable controlled
and Table 29: Read AC characteristics for details on the timings.
Table 31.
Write AC characteristics, chip enable controlled
M29DW127G
Symbol
Alt.
Parameter
Unit
60 ns (1)
70 ns
80 ns
tAVAV
tWC
Address Valid to Next Address Valid
Min
65
70
80
ns
tWLEL
tWS
Write Enable Low to Chip Enable Low
Min
0
0
0
ns
tELEH
tCP
Chip Enable Low to Chip Enable High
Min
35
35
35
ns
tDVEH
tDS
Input Valid to Chip Enable High
Min
45
45
45
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
0
0
ns
tEHWH
tWH
Chip Enable High to Write Enable High
Min
0
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
Min
30
30
30
ns
tAVEL
tAS
Address Valid to Chip Enable Low
Min
0
0
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
Min
45
45
45
ns
Output Enable High Chip Enable Low
Min
0
0
0
ns
tGHEL
1. Only available upon customer request.
74/95
M29DW127G
DC and AC parameters
Figure 23. Reset AC waveforms (no program/erase ongoing)
RB
E, G, W
tPHEL,
tPHGL
tPHWL
RP
tPLPX
AI11300c
Figure 24. Reset during program/erase operation AC waveforms
tPLYH
RB
tRHEL, tRHGL, tRHWL
E, G, W
RP
tPLPX
AI11301c
Table 32.
Reset AC characteristics
M29DW127G
Symbol
Alt.
tPLYH(1)
tREAD
tPLPX
tPHEL, tPHGL,
tPHWL (1)
Unit
60 ns
70 ns
80 ns
RP Low to read mode, during program or erase
Max
50
50
50
μs
tRP
RP pulse width
Min
10
10
10
μs
tRH
RP High to Write Enable Low, Chip Enable Low,
Output Enable Low
Min
50
50
50
ns
RP Low to standby mode, during read mode
Min
10
10
10
μs
RP Low to standby mode, during program or erase
Min
50
50
50
μs
RB High to Write Enable Low, Chip Enable Low,
Output Enable Low
Min
0
0
0
ns
Y
tRPD
tRHEL, tRHGL,
tRHWL (1)
Parameter
tRB
1. Sampled only, not 100% tested.
75/95
DC and AC parameters
M29DW127G
Figure 25. Accelerated program timing waveforms
VPPH
VPP/WP
VIL or VIH
tVHVPP
tVHVPP
AI05563
Figure 26. Data polling AC waveforms
tWHEH
tELQV
tEHQZ
tGHQZ
E
tGLQV
G
tWHGL2
W
tWHWH1 or tWHWH2
DQ7
DATA
DQ6-DQ0
DATA
DQ7
DQ6-DQ0=
Output flag
DQ7=
Valid data
DQ6-DQ0=
Valid data
Hi-Z
Hi-Z
tWHRL
R/B
AI13336c
1. DQ7 returns valid data bit when the ongoing Program or Erase command is completed.
2. See Table 33: Accelerated program and data polling/data toggle AC characteristics and Table 29: Read AC characteristics
for details on the timings.
76/95
M29DW127G
Table 33.
DC and AC parameters
Accelerated program and data polling/data toggle AC characteristics
M29DW127G
Symbol
Alt.
tVHVPP
Parameter
Unit
60 ns
70 ns
80 ns
VPP/WP raising and falling time
Min
250
250
250
ns
tAXGL
tASO
Address setup time to Output Enable Low during
toggle bit polling
Min
10
10
10
ns
tGHAX,
tEHAX
tAHT
Address hold time from Output Enable during toggle
bit polling
Min
10
10
10
ns
tEHEL2
tEPH
Chip Enable High during toggle bit polling
Min
10
10
10
ns
tWHGL2,
tGHGL2
tOEH
Output hold time during data and toggle bit polling
Min
20
20
20
ns
Max
30
30
30
ns
tWHRL
tBUSY Program/Erase Valid to RB Low
77/95
Package mechanical
12
M29DW127G
Package mechanical
To meet environmental requirements, Numonyx offers the M29DW127G in ECOPACK®
packages. ECOPACK packages are lead-free. The category of second level Interconnect is
marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
Figure 27. TSOP56 – 56 lead plastic thin small outline, 14 x 20 mm, package outline
1
56
e
B
D1
28
L1
29
A2
E1
E
A
A1
DIE
α
L
C
CP
TSOP-K
1. Drawing is not to scale.
Table 34.
TSOP56 – 56 lead plastic thin small outline, 14 x 20 mm, package
mechanical data
Millimeters
Inches
Symbol
Typ
Min
A
Typ
Min
1.20
Max
0.047
A1
0.10
0.05
0.15
0.004
0.002
0.006
A2
1.00
0.95
1.05
0.039
0.037
0.041
B
0.22
0.17
0.27
0.009
0.007
0.011
0.10
0.21
0.004
0.008
C
CP
78/95
Max
0.10
0.004
D1
14.00
13.90
14.10
0.551
0.547
0.555
E
20.00
19.80
20.20
0.787
0.780
0.795
E1
18.40
18.30
18.50
0.724
0.720
0.728
e
0.50
–
–
0.020
–
–
L
0.60
0.50
0.70
0.024
0.020
0.028
α
3
0
5
3
0
5
M29DW127G
Package mechanical
Figure 28. TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package outline
D
D1
FD
FE
E
SD
SE
E1
ddd
BALL "A1"
A
e
b
A2
A1
BGA-Z23
1. Drawing is not to scale.
Table 35.
TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package
mechanical data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.20
A1
0.30
A2
0.80
b
0.20
0.35
Max
0.047
0.012
0.008
0.014
0.014
0.020
0.031
0.35
0.50
D
10.00
9.90
10.10
0.394
0.390
0.398
D1
7.000
–
–
0.276
–
–
ddd
0.10
0.004
e
1.00
–
–
0.039
–
–
E
13.00
12.90
13.10
0.512
0.508
0.516
E1
7.00
–
–
0.276
–
–
FD
1.50
–
–
0.059
–
–
FE
3.00
–
–
0.118
–
–
SD
0.50
–
–
0.020
–
–
SE
0.50
–
–
0.020
–
–
79/95
Ordering information
13
Ordering information
Table 36.
Ordering information scheme
Example:
M29DW127G
M29 D
W 127G 60 NF 6
E
Device type
M29
Architecture
D = Dual operation
Operating voltage
W = VCC = 2.7 to 3.6 V
Device function
127G = 128 Mbit (8-Mbit x16 or 16-Mbit x8), page, dual boot
Speed
60= 60 ns (80 ns if VCCQ=1.65 V to VCC)(1)
70=70 ns (80 ns if V CCQ=1.65 V to VCC )
Package
NF = TSOP56: 14 x 20 mm
ZA = TBGA64: 10 x 13 mm - 1 mm pitch
Temperature range
6 = -40 to 85 °C
Option
E = ECOPACK package, standard packing
F = ECOPACK package, tape & reel packing
1. Only available upon customer request.
Note:
This product is also available with the extended block factory locked.
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest Numonyx sales office.
80/95
M29DW127G
Block addresses and read/modify protection groups
Appendix A
Table 37.
Bank
Bank A
Block addresses and read/modify protection
groups
Block addresses
Block
Protection group
Block size
(Kbytes/Kwords)
16-bit address range
(in hexadecimal)
0
Protection group
64/32
0000000–0007FFF
1
Protection group
64/32
0008000–000FFFF
2
Protection group
64/32
0010000–0017FFF
3
Protection group
64/32
0018000–001FFFF
4
Protection group
256/128
0020000–003FFFF
5
Protection group
256/128
0040000–005FFFF
6
Protection group
256/128
0060000–007FFFF
7
Protection group
256/128
0080000–009FFFF
8
Protection group
256/128
00A0000–00BFFFF
9
Protection group
256/128
00C0000–00DFFFF
10
Protection group
256/128
00E0000–00FFFFF
81/95
Block addresses and read/modify protection groups
Table 37.
Bank
Bank B
82/95
M29DW127G
Block addresses (continued)
Block
Protection group
Block size
(Kbytes/Kwords)
16-bit address range
(in hexadecimal)
11
Protection group
256/128
0100000–011FFFF
12
Protection group
256/128
0120000–013FFFF
13
Protection group
256/128
0140000–015FFFF
14
Protection group
256/128
0160000–017FFFF
15
Protection group
256/128
0180000–019FFFF
16
Protection group
256/128
01A0000–01BFFFF
17
Protection group
256/128
01C0000–01DFFFF
18
Protection group
256/128
01E0000–01FFFFF
19
Protection group
256/128
0200000–021FFFF
20
Protection group
256/128
0220000–023FFFF
21
Protection group
256/128
0240000–025FFFF
22
Protection group
256/128
0260000–027FFFF
23
Protection group
256/128
0280000–029FFFF
24
Protection group
256/128
02A0000–02BFFFF
25
Protection group
256/128
02C0000–02DFFFF
26
Protection group
256/128
02E0000–02FFFFF
27
Protection group
256/128
0300000–031FFFF
28
Protection group
256/128
0320000–033FFFF
29
Protection group
256/128
0340000–035FFFF
30
Protection group
256/128
0360000–037FFFF
31
Protection group
256/128
0380000–039FFFF
32
Protection group
256/128
03A0000–03BFFFF
33
Protection group
256/128
03C0000–03DFFFF
34
Protection group
256/128
03E0000–03FFFFF
M29DW127G
Table 37.
Bank
Bank C
Block addresses and read/modify protection groups
Block addresses (continued)
Block
Protection group
Block size
(Kbytes/Kwords)
16-bit address range
(in hexadecimal)
35
Protection group
256/128
0400000–041FFFF
36
Protection group
256/128
0420000–043FFFF
37
Protection group
256/128
0440000–045FFFF
38
Protection group
256/128
0460000–047FFFF
39
Protection group
256/128
0480000–049FFFF
40
Protection group
256/128
04A0000–04BFFFF
41
Protection group
256/128
04C0000–04DFFFF
42
Protection group
256/128
04E0000–04FFFFF
43
Protection group
256/128
0500000–051FFFF
44
Protection group
256/128
0520000–053FFFF
45
Protection group
256/128
0540000–055FFFF
46
Protection group
256/128
0560000–057FFFF
47
Protection group
256/128
0580000–059FFFF
48
Protection group
256/128
05A0000–05BFFFF
49
Protection group
256/128
05C0000–05DFFFF
50
Protection group
256/128
05E0000–05FFFFF
51
Protection group
256/128
0600000–061FFFF
52
Protection group
256/128
0620000–063FFFF
53
Protection group
256/128
0640000–065FFFF
54
Protection group
256/128
0660000–067FFFF
55
Protection group
256/128
0680000–069FFFF
56
Protection group
256/128
06A0000–06BFFFF
57
Protection group
256/128
06C0000–06DFFFF
58
Protection group
256/128
06E0000–06FFFFF
83/95
Block addresses and read/modify protection groups
Table 37.
Bank
Bank D
84/95
M29DW127G
Block addresses (continued)
Block
Protection group
Block size
(Kbytes/Kwords)
16-bit address range
(in hexadecimal)
59
Protection group
256/128
0700000–071FFFF
60
Protection group
256/128
0720000–073FFFF
61
Protection group
256/128
0740000–075FFFF
62
Protection group
256/128
0760000–077FFFF
63
Protection group
256/128
0780000–079FFFF
64
Protection group
256/128
07A0000–07BFFFF
65
Protection group
256/128
07C0000–07DFFFF
66
Protection group
64/32
07E0000–07E7FFF
67
Protection group
64/32
07E8000–07EFFFF
68
Protection group
64/32
07F0000–07F7FFF
69
Protection group
64/32
07F8000–07FFFFF
M29DW127G
Common flash interface (CFI)
Appendix B
Common flash interface (CFI)
The common flash interface is a JEDEC approved, standardized data structure that can be read from the
flash memory device. It allows a system software to query the device to determine various electrical and
timing parameters, density information and functions supported by the memory. The system can interface
easily with the device, enabling the software to upgrade itself when necessary.
When the Read CFI Query command is issued, the memory enters read CFI query mode and read
operations output the CFI data. Table 38, Table 39, Table 40, Table 41, Table 42 and Table 43 show the
addresses (A0-A7) used to retrieve the data. The CFI data structure also contains a security area where
a 64-bit unique security number is written (see Table 43: Security code area). This area can be accessed
only in read mode by the final user. It is impossible to change the security number after it has been
written by Numonyx.
Table 38.
Query structure overview(1)
Address
Sub-section name
Description
x16
x8
10h
20h
CFI query identification string
Command set ID and algorithm data offset
1Bh
36h
System interface information
Device timing & voltage information
27h
4Eh
Device geometry definition
Flash device layout
40h
80h
Primary algorithm-specific extended query
table
Additional information specific to the primary
algorithm (optional)
61h
C2h
Security code area
64-bit unique device number
1. Query data are always presented on the lowest order data outputs.
Table 39.
CFI query identification string(1)
Address
Data
x16
x8
10h
20h
0051h
11h
22h
0052h
12h
24h
0059h
13h
26h
0002h
14h
28h
0000h
15h
2Ah
0040h
16h
2Ch
0000h
17h
2Eh
0000h
18h
30h
0000h
19h
32h
0000h
1Ah
34h
0000h
Description
Value
‘Q’
Query unique ASCII string ‘QRY’
‘R’
‘Y’
Primary algorithm command set and control interface ID code 16 bit ID
code defining a specific algorithm
Address for primary algorithm extended query table (see Table 42)
Spansion
compatible
P = 40h
Alternate vendor command set and control interface ID code second
vendor - specified algorithm supported
NA
Address for alternate algorithm extended query table
NA
1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
85/95
Common flash interface (CFI)
M29DW127G
CFI query system interface information(1)
Table 40.
Address
Data
Description
Value
x16
x8
1Bh
36h
0027h
VCC logic supply minimum program/erase voltage
bit 7 to 4 value in volts
bit 3 to 0 value in 100 mV
2.7 V
1Ch
38h
0036h
VCC logic supply maximum program/erase voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV
3.6 V
1Dh
3Ah
00B5h
VPPH [programming] supply minimum program/erase voltage
bit 7 to 4 value in volts
bit 3 to 0 value in 100 mV
11.5 V
1Eh
3Ch
00C5h
VPPH [programming] supply maximum program/erase voltage
bit 7 to 4 value in volts
bit 3 to 0 value in 100 mV
12.5 V
1Fh
3Eh
0004h
1Fh 3Eh 0004h typical timeout for single byte/word program = 2n μs
16 μs
20h
40h
0004h
20h 40h 0004h typical timeout for minimum size write buffer program
= 2n μs
16 μs
21h
42h
000Ah
Typical timeout for individual block erase = 2n ms
22h
23h
44h
46h
0010h
0004h
n
Typical timeout for full Chip Erase = 2 ms
40 s
n
Maximum timeout for word program = 2 times typical
n
24h
48h
0004h
Maximum timeout for write buffer program = 2 times typical
25h
4Ah
0004h
Maximum timeout per individual block erase = 2 n times typical
26h
4Ch
0004h
Maximum timeout for Chip Erase =
1. The values given in the above table are valid for both packages.
86/95
2n
1s
times typical
200 μs
200 μs
4.6 s
400 s
M29DW127G
Table 41.
Common flash interface (CFI)
Device geometry definition
Address
Data
Description
Value
x16
x8
27h
4Eh
0018h
Device size = 2n in number of bytes
16 Mbytes
28h
29h
50h
52h
0002h
0000h
Flash device interface code description
x8,
x16 async.
2Ah
2Bh
54h
56h
0006h
0000h
Maximum number of bytes in multiple-byte program or page= 2n
64
2Ch
58h
0003h
Number of erase block regions. It specifies the number of regions
containing contiguous erase blocks of the same size.
3
2Dh
2Eh
5Ah
5Ch
0003h
0000h
Erase block region 1 information
2Dh-2Eh: number of erase blocks of identical size.
4 blocks
64 Kbytes
2Fh
30h
5Eh
60h
0000h
0001h
Erase block region 1 information
2Fh-30h: block size (n*256 bytes)
4 blocks
64 Kbytes
31h
32h
33h
34h
62h
64h
66h
68h
003Dh
0000h
0000h
0004h
Erase block region 2 information
62 blocks
256 Kbytes
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0003h
0000h
0000h
0001h
Erase block region 3 information
4 blocks
64 Kbytes
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase block region 4 information
NA
87/95
Common flash interface (CFI)
M29DW127G
Primary algorithm-specific extended query table (1)
Table 42.
Address
Data
Description
Value
x16
x8
40h
80h
0050h
41h
82h
0052h
42h
84h
0049h
43h
86h
0031h
Major version number, ASCII
‘1’
44h
88h
0033h
Minor version number, ASCII
‘3’
45h
8Ah
000Dh
Address sensitive unlock (bits 1 to 0)
00 = required, 01= not required
Silicon revision number (bits 7 to 2)
46h
8Ch
0002h
Erase Suspend
00 = not supported, 01 = read only, 02 = read and write
2
47h
8Eh
0001h
Block protection
00 = not supported, x = number of blocks per group
1
48h
90h
0000h
Temporary block unprotect
00 = not supported, 01 = supported
49h
92h
0008h
Block protect /unprotect
08 = M29DW127G
8
4Ah
94h
003Bh
Simultaneous operations: x= block number (excluding bank A)
59
4Bh
96h
0000h
Burst mode, 00 = not supported, 01 = supported
4Ch
98h
0002h
Page mode, 00 = not supported, 02 = 8-word page
4Dh
9Ah
00B5h
VPPH [programming/erasing] supply minimum program/erase voltage
bit 7 to 4 value in volts
bit 3 to 0 value in 100 mV
11.5 V
4Eh
9Ch
00C5h
VPPH [programming/erasing] supply maximum program/erase voltage
bit 7 to 4 value in volts
bit 3 to 0 value in 100 mV
12.5 V
4Fh
9Eh
0001h
01 = dual boot
Dual boot
50h
A0h
0001h
Program suspend, 00 = not supported, 01 = supported
Supported
51h
A2h
0001h
Unlock bypass: 00 = not supported, 01 = supported
Supported
52h
A4h
0008h
Extended memory block size (customer lockable), 2n bytes
256
57h
AEh
0004h
Bank organization, 00 = data at 4Ah is 0, x= bank number
4
58h
B0h
000Bh
Bank A information, x = number of blocks in bank A
11
59h
B2h
0018h
Bank B information, x = number of blocks in bank B
24
5Ah
B4h
0018h
Bank C information, x = number of blocks in bank C
24
5Bh
B6h
000Bh
Bank D information, x = number of blocks in bank D
11
‘P’
Primary algorithm extended query table unique ASCII string ‘PRI’
‘I’
1. The values given in the above table are valid for both packages.
88/95
‘R’
Yes,
90 nm
Not
supported
Not
supported
Yes
M29DW127G
Table 43.
Common flash interface (CFI)
Security code area
Address
Data
Description
C3h, C2h
XXXX
XXXX
62h
C5h, C4h
XXXX
XXXX
63h
C7h, C6h
XXXX
XXXX
64h
C9h, C8h
XXXX
XXXX
x16
x8
61h
Value
64 bit: unique device number
89/95
Extended memory block
Appendix C
M29DW127G
Extended memory block
The M29DW127G has an extra block, the extended memory block, that can be accessed
using a dedicated command. This extended memory block is 256 words (x16 mode) and
512 bytes (x8 mode). It is used as a security block (to provide a permanent security
identification number) or to store additional information.
The extended memory block is divided into two memory areas of 256 bytes / 128 words
each:
The first one is factory locked.
The second one is customer lockable. It is up to the customer to protect it from program
operations. Its status is indicated by bit DQ6 and DQ7. When DQ7 is set to ‘1’ and DQ6
to ‘0’, it indicates that this second memory area is customer lockable. When DQ7 and
DQ6 are both set to ‘1’, it indicates that the second part of the extended memory block
is customer locked and protected from program operations.
Bits DQ6 and DQ7 are the most significant bits in the extended block protection indicator
and a specific procedure must be followed to read it. See Section 4.2: Verify extended
memory block protection indicator and Table 9: Block protection (16-bit mode) for details of
how to read bit DQ7.
The extended memory block can only be accessed when the device is in extended block
mode. For details of how the extended block mode is entered and exited, refer to the
Section 7.1.10: Program command and Section 7.3.2: Exit Extended Memory Block
command, and to Table 17: Block protection commands (16-bit mode).
C.1
Factory locked section of extended memory block
The first section of the extended memory block is permanently protected from program
operations and cannot be unprotected. The random number, electronic serial number (ESN)
and security identification number (see Table 44: Extended memory block address and
data) are written in this section in the factory.
90/95
M29DW127G
C.2
Extended memory block
Customer lockable section of extended memory block
The device is delivered with the second section of the extended memory block ‘customer lockable’: bits
DQ7 and DQ6 are set to '1' and '0' respectively. It is up to the customer to program and protect this
section of the extended memory block but care must be taken because the protection is not reversible.
This section can be protected by setting the extended memory block protection bit, DQ0, to ‘0’.
Bit DQ6 of the extended block protection indicator is automatically set to '1' to indicate that the second
section of the extended memory block is customer locked.
Once the extended memory block is programmed and protected, the Exit Extended Block command
must be issued to exit the extended block mode and return the device to read mode.
Table 44.
Extended memory block address and data
Device
M29DW127G
Data
Address(1)
Factory locked
Customer lockable
000000h-00007Fh
Random number, ESN(2) ,
security identification number
Unavailable
000080h-0000FFh
Unavailable
Determined by customer
1. See Table 37: Block addresses.
2. ESN = electronic serial number.
91/95
Flowcharts
Appendix D
M29DW127G
Flowcharts
Figure 29. Write to buffer program flowchart and pseudocode
Start
Write to Buffer
command,
block address
Write n(1),
block address
First three cycles of the
Write to Buffer and Program command
Write Buffer Data,
start address
X=n
YES
X=0
NO
Abort Write
to Buffer
YES
Write to a different
block address
NO
Write Next Data,(3)
Program Address Pair
Write to Buffer and
Program Aborted(2)
X = X-1
Write to Buffer Program
Confirm, block address
Read Status Register
(DQ1, DQ5, DQ7) at
last loaded address
YES
DQ7 = Data
NO
NO
DQ1 = 1
NO
DQ5 = 1
YES
YES
Check Status Register
(DQ5, DQ7) at
last loaded address
DQ7 = Data
YES
(4)
NO
FAIL OR ABORT(5)
END
AI08968b
1. n+1 is the number of addresses to be programmed.
2. A write to buffer program abort and reset must be issued to return the device in read mode.
3. When the block address is specified, any address in the selected block address space is acceptable. However when
loading write buffer address with data, all addresses must fall within the selected write buffer page.
4. DQ7 must be checked since DQ5 and DQ7 may change simultaneously.
5. If this flowchart location is reached because DQ5=’1’, then the Write to Buffer Program command failed. If this flowchart
location is reached because DQ1=’1’, then the Write to Buffer Program command aborted. In both cases, the appropriate
Reset command must be issued to return the device in read mode: a Reset command if the operation failed, a Write to
Buffer Program Abort and Reset command if the operation aborted.
6. See Table 12: Standard commands (16-bit mode), for details on Write to Buffer Program command sequence.
92/95
M29DW127G
Flowcharts
Figure 30. Enhanced buffered program flowchart and pseudocode
Start
Enhanced Buffered
Program command,
block address
First three cycles of the
Enhanced Buffered Program command
Write Buffer Data,
start address (00),
X=255
YES
X=0
NO
Abort Write
to Buffer
YES
Write to a different
block address
NO
Write Next Data,(2)
Program Address Pair
Enhanced Buffered
Program Aborted(1)
X = X-1
Enhanced Buffered
Program Confirm,
block address
Read Status Register
(DQ1, DQ5, DQ7) at
last loaded address
YES
DQ7 = Data
NO
NO
DQ1 = 1
YES
NO
DQ5 = 1
YES
Check Status Register
(DQ5, DQ7) at
last loaded address
DQ7 = Data
YES
(3)
NO
FAIL OR ABORT(4)
END
AI14243
1. A buffered program abort and reset must be issued to return the device in read mode.
2. When the block address is specified, all the addresses in the selected block address space must be issued starting from
(00). Furthermore, when loading write buffer address with data, data program addresses must be consecutive.
3. DQ7 must be checked since DQ5 and DQ7 may change simultaneously.
4. If this flowchart location is reached because DQ5=’1’, then the Enhanced Buffered Program command failed. If this
flowchart location is reached because DQ1=’1’, then the Enhanced Buffered Program command aborted. In both cases, the
appropriate reset command must be issued to return the device in read mode: a Reset command if the operation failed, a
Buffered Program Abort and Reset command if the operation aborted.
5. See Table 15: Enhanced buffered program commands, for details on Enhanced Buffered Program command sequence.
93/95
Revision history
14
Revision history
Table 45.
94/95
M29DW127G
Document revision history
Date
Version
Revision details
20-Oct-2008
1
Initial release.
28-Oct-2008
2
Revised the Appendix B: Common flash interface (CFI) to include both
x16 and x8 information.
Revised the following data in Table 40: CFI query system interface
information:
– at address 1Dh changed data column from 0085h to 00B5h and value
column from 8.5 V to 11.5 V.
– at address 1Eh changed data column 0095h to 00C5h and value
column from 9.5 V to 12.5 V.
Revised the following data in In Table 42: Primary algorithm-specific
extended query table:
– at address 4Dh changed data column from 0085h to 00B5h and value
column from 8.5 V to 11.5 V.
– at address 4Eh changed data column 0095h to 00C5h and value
column from 9.5 V to 12.5 V.
5-May-2009
3
Corrected order information table.
M29W128GH, M29W128GL
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NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
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Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
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these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
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95/95
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